Semiconductor Device and Radio Frequency Module Formed on High Resistivity Substrate

• US 20160372592A1
• Filed: 02/11/2016
• Published: 12/22/2016
• Est. Priority Date: 06/18/2015
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Cho, Yong Soo
• Granted Patent: US 9,755,068 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

In embodiments, a semiconductor device includes a high resistivity substrate, a transistor disposed on the high resistivity substrate, and a deep trench device isolation region disposed in the high resistivity substrate to surround the transistor. Particularly, the high resistivity substrate has a first conductive type, and a deep well region having a second conductive type is disposed in the high resistivity substrate. Further, a first well region having the first conductive type is disposed on the deep well region, and the transistor is disposed on the first well region.

Claims

1. A semiconductor device comprising:

a high resistivity substrate;

a transistor disposed on the high resistivity substrate; and

a deep trench device isolation region disposed in the high resistivity substrate to surround the transistor.

2. The semiconductor device of claim 1, further comprising:

a shallow trench device isolation region disposed on the deep trench device isolation region.

3. The semiconductor device of claim 1, wherein the transistor comprises:

a gate structure disposed on the high resistivity substrate;

a source region and a drain region disposed at surface portions of the high resistivity substrate adjacent to both sides of the gate structure, respectively; and

a high concentration impurity region disposed on one side of the source region.

4. The semiconductor device of claim 3, wherein the source region has a second conductive type;

the high concentration impurity region has a first conductive type; and

the source region and the high concentration impurity region are electrically connected with each other.

5. The semiconductor device of claim 1, wherein the high resistivity substrate has a first conductive type;

a deep well region having a second conductive type is disposed in the high resistivity substrate;

a first well region having the first conductive type is disposed on the deep well region; and

wherein the transistor is disposed on the first well region.

6. The semiconductor device of claim 5, wherein the deep well region and the first well region are disposed inside the deep trench device isolation region, and wherein the deep trench device isolation region is formed deeper than the deep well region.

7. The semiconductor device of claim 5, wherein a second well region having the first conductive type is disposed outside the deep trench device isolation region, and wherein a second high concentration impurity region having the first conductive type is disposed on the second well region.

8. The semiconductor device of claim 5, wherein the deep well region is disposed wider than the first well region, and the deep trench device isolation region extends through the deep well region so as to be deeper than the deep well region.

9. The semiconductor device of claim 6, wherein a second well region having the second conductive type is disposed outside the deep trench device isolation region;

and a second high concentration impurity region having the second conductive type is disposed on the second well region.

10. The semiconductor device of claim 9, wherein the deep trench device isolation region has a slit to electrically connect the deep well region with the second well region.

11. The semiconductor device of claim 9, wherein a third well region having the first conductive type is disposed outside the second well region.

12. The semiconductor device of claim 9, wherein a second device isolation region is disposed to surround the second well region and the second high concentration impurity region.

13. The semiconductor device of claim 12, wherein the second device isolation region comprises:

a second deep trench device isolation region disposed to surround the second well region; and

a second shallow trench device isolation region disposed on the second deep trench device isolation region.

14. The semiconductor device of claim 12, wherein a third well region having the first conductive type is disposed outside the second device isolation region.

15. A semiconductor device comprising:

a high resistivity substrate having a first conductive type;

a deep well region having a second conductive type and disposed in the high resistivity substrate;

a first well region having the first conductive type and disposed on the deep well region;

a plurality of transistors disposed on the first well region; and

a deep trench device isolation region having a ring shape to surround the plurality of transistors and disposed deeper than the deep well region.

16. The semiconductor device of claim 15, wherein the plurality of transistors is disposed in a multi-finger structure in which the plurality of transistors is electrically connected with one another.

17. The semiconductor device of claim 16, wherein a high concentration impurity region having the first conductive type is disposed between source regions of transistors disposed adjacent with each other among the plurality of transistors;

and

the high concentration impurity region and the source regions of the adjacent transistors are electrically connected with one another.

18. The semiconductor device of claim 15, wherein a second well region having the second conductive type is disposed outside the deep trench device isolation region;

a second high concentration impurity region having the second conductive type is disposed on the second well region; and

the deep trench device isolation region has a slit to electrically connect the deep well region with the second well region.

19. The semiconductor device of claim 18, wherein a second deep trench device isolation region is disposed outside the second well region;

a third well region having the first conductive type is disposed outside the second deep trench device isolation region; and

a third high concentration impurity region having the first conductive type is disposed on the third well region.

20. A radio frequency (RF) module comprising:

an RF switching device disposed on a high resistivity substrate;

an RF active device disposed on the high resistivity substrate;

an RF passive device disposed on the high resistivity substrate; and

a control device disposed on the high resistivity substrate,

wherein at least one of the RF switching device and the RF active device comprises;

a transistor disposed on the high resistivity substrate; and

a deep trench device isolation region disposed in the high resistivity substrate to surround the transistor.