THIN-FILM TRANSISTOR ELEMENT, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE

• US 20160372605A1
• Filed: 06/20/2014
• Published: 12/22/2016
• Est. Priority Date: 07/05/2013
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: JOLED Inc.
• Inventors: YOSHITANI, Toshiaki, KISHIDA, Yuji
• Granted Patent: US 9,508,866 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin-film transistor includes: a gate electrode; a channel layer not adjacent to the gate electrode; a channel protection layer exposing portion of the channel layer, a source electrode contacting the channel layer at portion of an exposed portion of the channel layer, and a drain electrode contacting the channel layer at portion of the exposed portion, in respective order. The channel layer includes oxide semiconductor. Surface of the channel protection layer includes upper surface and side surface extending from the upper surface to the exposed portion. The drain electrode has: a rising portion extending from above the exposed region to the channel layer along the side surface; and an upper surface covering portion continuous with the rising portion and extending onto portion of the upper surface. The upper surface covering portion has a facing portion facing a channel region and being 2.5 μm or less in channel length direction.

Claims

1-10. -10. (canceled)

11. A thin-film transistor comprising:

a gate electrode;

a channel layer disposed above the gate electrode and not adjacent to the gate electrode;

a channel protection layer covering a portion of the channel layer and exposing a portion of the channel layer;

a source electrode that is in contact with the channel layer at a source contact region that is a portion of an exposed portion of the channel layer; and

a drain electrode that is not adjacent to the source electrode and is in contact with the channel layer at a drain contact region that is a portion of the exposed portion, the drain contact portion being different from the source contact region, wherein

the channel layer includes oxide semiconductor,

a surface of the channel protection layer includes an upper surface and a side surface that extends from the upper surface to the exposed portion,

the drain electrode has;

a rising portion that extends from above the drain contact region to the channel layer along the side surface of the channel protection layer; and

an upper surface covering portion that is continuous with the rising portion and extends onto a portion of the upper surface of the channel protection layer,

the upper surface covering portion has a facing portion that faces a channel region that is a region of the channel layer interposed between the source contact region and the drain contact region, and

the facing portion has a length that is smaller than or equal to 2.5 μ

m in a channel length direction in which a straight line that connects the source contact region with the drain contact region along a shortest distance therebetween extends.

12. The thin-film transistor according to claim 11, wherein

the facing portion has a length that is no smaller than 2.0 μ

m in the channel length direction.

13. The thin-film transistor according to claim 11, wherein

a carrier mobility in the channel region of the thin-film transistor is lower than or equal to 13 cm²/(V·

s).

14. A display device comprising a plurality of thin-film transistors according to claim 11.

15. The display device according to claim 14, wherein

an average value of a carrier mobility in the respective channel regions of the plurality of thin-film transistors is lower than or equal to 13 cm²/(V·

s).

16. A method for manufacturing a thin-film transistor, comprising:

forming a gate electrode;

forming a channel layer above the gate electrode so as not to be adjacent to the gate electrode;

forming a channel protection layer so as to cover a portion of the channel layer and expose a portion of the channel layer;

forming a source electrode so as to be in contact with the channel layer at a source contact region that is a portion of an exposed portion of the channel layer; and

forming a drain electrode so as not to be adjacent to the source electrode and be in contact with the channel layer at a drain contact region that is a portion of the exposed portion, the drain contact portion being different from the source contact region, wherein

in forming the channel layer, oxide semiconductor is used for forming the channel layer,

in forming the channel protection layer, an upper surface and a side surface that extends from the upper surface to the exposed portion are formed as a surface of the channel protection layer,

in forming the drain electrode, the drain electrode is formed so as to have a rising portion and an upper surface covering portion, the rising portion extending from above the drain contact region to the channel layer along the side surface of the channel protection layer, the upper surface covering portion being continuous with the rising portion, extending onto a portion of the upper surface of the channel protection layer, and having a facing portion that faces a channel region that is a region of the channel layer interposed between the source contact region and the drain contact region, the facing portion having a length that is smaller than or equal to 2.5 μ

m in a channel length direction in which a straight line that connects the source contact region with the drain contact region along a shortest distance therebetween extends.

17. The method for manufacturing a thin-film transistor according to claim 16, wherein

when the drain electrode is formed, the facing portion is formed so as to have a length that is no smaller than 2.0 μ

m in the channel length direction.

18. A thin-film transistor comprising:

a gate electrode;

a channel layer disposed above the gate electrode and not adjacent to the gate electrode;

a channel protection layer covering a portion of the channel layer and exposing a portion of the channel layer;

a source electrode that is in contact with the channel layer at a source contact region that is a portion of an exposed portion of the channel layer; and

a drain electrode that is not adjacent to the source electrode and is in contact with the channel layer at a drain contact region that is a portion of the exposed portion, the drain contact portion being different from the source contact region, wherein

the channel layer includes oxide semiconductor,

a surface of the channel protection layer includes an upper surface and a side surface that extends from the upper surface to the exposed portion,

the drain electrode has;

a rising portion that extends from above the drain contact region to the channel layer along the side surface of the channel protection layer, and

an upper surface covering portion that is continuous with the rising portion and extends onto a portion of the upper surface of the channel protection layer,

the upper surface covering portion has a facing portion that faces a channel region that is a region of the channel layer interposed between the source contact region and the drain contact region,

the facing portion has a length that is smaller than or equal to 2.5 μ

m in a channel length direction in which a straight line that connects the source contact region with the drain contact region along a shortest distance therebetween extends, and

in an xy coordinate system in which points are expressed with coordinates (x, y), a point (W3, T3) is located within a range that is surrounded by a line that connects points (2.00,

     209), (2.33,

     219), (2.43,

     234), (3.29,

     291), (3.49,

     360), and (4.00,

     480), a straight line that connects points (2.00,

     209) and (2.00,

     480), and a straight line that connects points (2.00,

     480) and (4.00,

     480), where W3 (μ

m) denotes a length of the facing portion in a channel length direction in which a straight line that connects the source contact region with the drain contact region along a shortest distance therebetween extends, and T3 (nm) denotes a shortest distance between the channel layer and the facing portion.

19. The thin-film transistor according to claim 18, wherein

in the xy coordinate system, the point (W3, T3) is located within a range that is surrounded by a line that connects points (2.00, 344), (2.06, 341), (2.97, 352), (3.02, 356), (3.22, 390), and (3.48, 480), a straight line that connects points (2.00, 344) and (2.00, 480), and a straight line that connects points (2.00, 480) and (3.48, 480).

20. A display device comprising a plurality of thin-film transistors according to claim 18.