Sampling/Quantization Converters

• US 20160373125A1
• Filed: 08/30/2016
• Published: 12/22/2016
• Est. Priority Date: 02/11/2015
• Status: Active Grant

• Current Assignee: Pagnanelli Family Trust
• Original Assignee: Syntropy Systems, Llc
• Inventors: Pagnanelli, Christopher
• Granted Patent: US 9,621,175 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03M 3/404 characterised by the type of bandpass filters used
• CPC Class Codes: H03M 3/422 having one quantiser only
• CPC Class Codes: H03M 3/436 characterised by the order of the loop filter, e.g. error feedback type
• CPC Class Codes: H03M 3/468 Interleaved, i.e. using multiple converters or converter parts for one channel, e.g. using Hadamard codes, pi-delta-sigma converters

Abstract

Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches, with each of the processing branches including a bandpass noise-shaping circuit, a sampling/quantization circuit coupled to an output of the bandpass noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the sampling/quantization converter circuit back into the bandpass noise-shaping circuit. A center frequency of the digital bandpass filter in each processing branch corresponds to a stopband region in a quantization noise transfer function for the bandpass noise-shaping circuit in the same processing branch.

Claims

1. An apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, comprising:

an input line for accepting an input signal that is continuous in time and continuously variable;

a plurality of processing branches coupled to the input line, each of said processing branches including;

(a) a bandpass noise-shaping circuit, (b) a sampling/quantization circuit coupled to an output of the bandpass noise-shaping circuit, (c) a digital bandpass filter coupled to an output of the sampling/quantization circuit, and (d) a line coupling the output of the sampling/quantization circuit back into the bandpass noise-shaping circuit; and

an adder coupled to outputs of the plurality of processing branches,

wherein a center frequency of the digital bandpass filter in each said processing branch corresponds to a stopband region in a quantization noise transfer function for the bandpass noise-shaping circuit in the same processing branch,

wherein each of said digital bandpass filters includes;

(a) a quadrature frequency downconverter that has in-phase and quadrature outputs, (b) a first lowpass filter coupled to the in-phase output of the quadrature frequency downconverter, (c) a second lowpass filter coupled to the quadrature output of the quadrature frequency downconverter, and (d) a quadrature frequency upconverter coupled to outputs of the first and second lowpass filters, and

wherein a frequency response of each of said first and second lowpass filters has a magnitude that varies approximately with frequency according to a product of raised sin(x)/x functions.

2. An apparatus according to claim 1, wherein at least one of the sin(x)/x functions is raised to a power that is equal to one.

3. An apparatus according to claim 1, wherein at least one of the sin(x)/x functions is raised to a power that is greater than one.

4. An apparatus according to claim 1, wherein the frequency response of at least one of said first or said second lowpass filters has a magnitude that varies approximately with frequency according to the product of a raised sin (x₁)/x₁ function and a raised sin (x₂)/x₂, where x₁≠

x₂.

5. An apparatus according to claim 4, wherein x₁≧

2x₂.

6. An apparatus according to claim 1, wherein at least one of the lowpass filters has an impulse response length that is less than 9/2·

M·

N/f_S seconds, where M is a number of processing branches for said apparatus, N is an excess oversampling rate for said apparatus, and f_S is a sampling rate for said apparatus.

7. An apparatus according to claim 1, wherein said quadrature frequency upconverter utilizes a quadrature multiplier to shift baseband outputs of said first and second lowpass filters to a center frequency other than zero hertz, and wherein the outputs of said first and second lowpass filters are combined to form a real output signal.

8. An apparatus according to claim 1, wherein said quadrature frequency upconverter utilizes a complex multiplier to shift baseband outputs of said first and second lowpass filters to a center frequency other than zero hertz, and wherein the outputs of said first and second lowpass filters are combined to form a complex output signal represented by in-phase and quadrature components.

9. An apparatus according to claim 1, wherein said quadrature frequency downconverter utilizes a quadrature multiplier to convert a real-valued input signal into a baseband output having in-phase and quadrature components.

10. An apparatus according to claim 1, wherein said quadrature frequency downconverter utilizes a complex multiplier to convert a complex-valued input signal, represented by in-phase and quadrature components, into a baseband output having in-phase and quadrature components.

11. An apparatus according to claim 1, wherein at least one of the lowpass filters is implemented as a recursive structure.

12. An apparatus according to claim 1, wherein at least one of the lowpass filters is comprised of at least one moving-average component.

13. An apparatus according to claim 1, wherein a bandwidth of at least one of the first and second lowpass filters is independently programmable to vary a bandwidth of a corresponding one of the digital bandpass filters.

14. An apparatus according to claim 1, wherein at least one of the digital bandpass filters is implemented as a polyphase decomposition structure.

15. An apparatus according to claim 14, wherein a polyphase decomposition factor, m, of the polyphase decomposition structure is a submultiple of the total number of processing branches, M

16. An apparatus according to claim 12, wherein at least one of the lowpass filters is comprised of a number of cascaded moving-average filter stages, wherein each of said lowpass filters has an impulse response length that is less than 9/2·

M·

N periods of the sampling clock, where M is a number of processing branches for said apparatus and N is an excess oversampling rate for said apparatus.

17. An apparatus according to claim 12, wherein at least one of the lowpass filters is comprised of a number of cascaded moving-average filter stages, wherein each of the stages averages the same number of samples, and wherein the number of stages is greater than one and other than one plus an effective noise-shaping order of the bandpass noise-shaping circuit response.

18. An apparatus according to claim 17, wherein said at least one of the lowpass filters is comprised of cascaded moving-average filter stages that collectively provide spectral minima at frequencies other than multiples of a conversion rate of said apparatus.

19. An apparatus according to claim 17, wherein the number of moving-average filter stages is zero, two, three, or four plus an effective noise-shaping order of a response of the bandpass noise-shaping circuit.

20. An apparatus according to claim 12, wherein said at least one of the lowpass filters is comprised of cascaded moving-average filter stages, and wherein at least one of the stages averages a number of samples that is different by more than one from a number of samples averaged by at least one of the other stages.

21. An apparatus according to claim 1, wherein the digital bandpass filter further includes an equalizer.

22. An apparatus according to claim 21, wherein the equalizer has a single complex tap.

23. An apparatus according to claim 21, wherein the equalizer has a single real tap.

24. An apparatus according to claim 21, wherein the equalizer has plural complex taps.

25. An apparatus according to claim 21, wherein the equalizer has plural real taps.

26. An apparatus according to claim 1, wherein sine and cosine sequences are used by the quadrature frequency downconverter and the quadrature frequency upconverter for quadrature downconversion and upconversion, respectively, and are generated through direct digital synthesis using digital accumulators and sinusoid lookup.

27. An apparatus according to claim 1, wherein sine and cosine sequences are used by the quadrature frequency downconverter and the quadrature frequency upconverter for quadrature downconversion and upconversion, respectively, and are generated using recursive structures.

28. An apparatus according to claim 1, wherein sine and cosine sequences are used by the frequency downconverter and the frequency upconverter for quadrature downconversion and upconversion, respectively, and wherein at least one of an amplitude or phase of the sine and cosine sequences is adjustable.

29. An apparatus according to claim 1, wherein sine and cosine sequences are used by the frequency downconverter and the frequency upconverter for quadrature downconversion and upconversion, respectively, and wherein the period of the sine and cosine sequences is adjustable.

30. An apparatus according to claim 1, further comprising a configuration means for converting a first signal sample rate generated by the sampling/quantization circuit in at least one of the various processing branches to a second signal sample rate that is different than the first signal sample rate.

31. An apparatus according to claim 30, wherein the configuration means includes the application of a phase rotation to complex-valued data samples based on a variable interpolant value.

32. An apparatus according to claim 30, wherein the configuration means includes at least one digital interpolator that alters an effective sampling phase based on a variable interpolant value.

33. An apparatus according to claim 31, wherein interpolation used by the at least one digital interpolator is at least second-order.

34. An apparatus according to claim 31, wherein interpolation used by the at least one digital interpolator is first-order.

35. An apparatus according to claim 31, wherein the at least one digital interpolator is implemented as a polyphase decomposition structure.

36. An apparatus according to claim 31, wherein an interpolant used by the at least one digital interpolator is generated using a numerically-controlled oscillator.

37. An apparatus according to claim 1, wherein a configuration means is provided to enable plural modes of operation, including:

(i) a mode for operation as a single, wideband converter with high output data rate, and (ii) a mode for operation as plural, independent converters having an arbitrary mix of narrowband and wideband outputs at various sample rates.

38. An apparatus according to claim 37, wherein the configuration means comprises an add-multiplex array.

39. An apparatus according to claim 37, wherein the number of processing branches M is a power of two.

40. An apparatus according to claim 1, wherein each of a plurality of the processing branches includes at least one quadrature downconverter that decreases, by a factor of at least two, a center frequency of the frequency band selected for said processing branch.

41. An apparatus according to claim 40, wherein the digital bandpass filter includes at least one of a downconverter and an upconverter having at least one parameter that can be adjusted to compensate for at least one of amplitude or phase imbalance of the quadrature frequency downconverter.

42. An apparatus according to claim 1, wherein the sampling/quantization circuit in each of a plurality of said processing branches is a single-bit quantizer.

43. An apparatus according to claim 1, wherein the sampling/quantization circuit is a multi-bit quantizer.

44. An apparatus according to claim 43, wherein the bandpass noise-shaping circuit includes a nonlinear bit-mapping component that converts a binary-weighted, digital input to a higher-precision digital output having other than perfect binary weighting.

45. An apparatus according to claim 44, wherein the nonlinear bit-mapping component applies input-bit weighting factors to the digital input and at least one of the input-bit weighting factors applied by the nonlinear bit-mapping component is programmable.

46. An apparatus according to claim 45, wherein the input-bit weighting factors are independently adjusted to minimize at least one of a mean absolute value or a variance of a residual quantization noise of the bandpass quantization-noise-shaping circuit.

47. An apparatus according to claim 1, further comprising within each of said plurality of processing branches:

at least one additional sampling/quantization circuit coupled to the output of the bandpass noise-shaping circuit;

a second adder coupled to an output of each sampling/quantization circuit; and

a line coupling an output of the second adder back into said bandpass noise-shaping circuit,

wherein each of said sampling/quantization circuits operates at a subsampling rate which is less than a final sampling rate of said apparatus,

wherein each of said sampling/quantization circuits subsamples on a different phase of a subsampling clock, such that subsampling instants associated with each of said sampling/quantization circuits are offset in time by increments which are integer multiples of a period corresponding to said final sampling rate, and

wherein said second adder sums the subsampled outputs of said sampling/quantization circuits to produce a filter response that includes a lowpass function having a bandwidth smaller than one-half of said final sampling rate.

48. An apparatus according to claim 47, wherein said final sampling rate is at least twice a maximum frequency component associated with said continuous-time input signal.

49. An apparatus according to claim 47, wherein said second adder sums the outputs of said sampling/quantization circuits to produce a filter response which is at least approximately equal to that of a zero-order hold at said subsampling rate.