HARDWARE APPARATUSES AND METHODS TO PERFORM TRANSACTIONAL POWER MANAGEMENT

• US 20160378160A1
• Filed: 06/27/2015
• Published: 12/29/2016
• Est. Priority Date: 06/27/2015
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Krishnakumar, Nivedha, Muralidhar, Rajeev D., Seshadri, Harinarayanan, Singh, Youvedeep, Partiwala, Suketu R.
• Granted Patent: US 9,733,689 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

Claims

1. A hardware apparatus comprising:

a hardware processor having a core;

a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain; and

a power transaction unit to;

assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution,

perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and

perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

2. The hardware apparatus of claim 1, wherein the first power transaction and the second power transaction each include multiple instructions.

3. The hardware apparatus of claim 1, further comprising a plurality of power state registers to receive the power management command for each domain.

4. The hardware apparatus of claim 3, wherein the conflict is the first power transaction to write to a power state register that the second power transaction has written.

5. The hardware apparatus of claim 1, wherein the power transaction unit is to not issue a lock.

6. The hardware apparatus of claim 1, wherein the conflict is the first power transaction and the second power transaction to write conflicting power management commands for a shared power domain.

7. The hardware apparatus of claim 1, wherein, when there is the conflict, a transition of a power domain in response to execution of the second power transaction is only visible to other transactions after the commit of the second power transaction.

8. The hardware apparatus of claim 1, further comprising a memory transaction unit to perform a commit of a first thread and a second thread after concurrent execution of the first thread on the core and the second thread on a second core of the hardware processor unless the first thread and the second thread are to modify a same memory address.

9. A method comprising:

providing a plurality of power domains of a hardware apparatus including a hardware processor to transition to one of a plurality of power states in response to a power management command for each power domain;

assigning a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution;

performing a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction; and

performing an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

10. The method of claim 9, wherein the first power transaction and the second power transaction each include multiple instructions.

11. The method of claim 9, further comprising receiving the power management command for each domain at a power state register.

12. The method of claim 11, wherein the conflict is the first power transaction writing to a power state register that the second power transaction has written.

13. The method of claim 9, wherein no lock is issued.

14. The method of claim 9, wherein the conflict is the first power transaction and the second power transaction writing conflicting power management commands for a shared power domain.

15. The method of claim 9, wherein, when there is the conflict, a transition of a power domain in response to execution of the second power transaction is only visible to other transactions after the commit of the second power transaction is performed.

16. The method of claim 9, further comprising performing a commit of a first thread and a second thread after concurrent execution of the first thread and the second thread on the hardware processor unless the first thread and the second thread are to modify a same memory address.

17. A non-transitory machine readable storage medium having stored program code that when processed by a machine causes a method to be performed, the method comprising:

providing a plurality of power domains of a hardware apparatus including a hardware processor to transition to one of a plurality of power states in response to a power management command for each power domain;

assigning a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution;

performing a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction; and

performing an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

18. The non-transitory machine readable storage medium of claim 17, wherein the first power transaction and the second power transaction each include multiple instructions.

19. The non-transitory machine readable storage medium of claim 17, wherein the method further comprises receiving the power management command for each domain at a power state register.

20. The non-transitory machine readable storage medium of claim 19, wherein the conflict is the first power transaction writing to a power state register that the second power transaction has written.

21. The non-transitory machine readable storage medium of claim 17, wherein the method includes no lock being issued.

22. The non-transitory machine readable storage medium of claim 17, wherein the conflict is the first power transaction and the second power transaction writing conflicting power management commands for a shared power domain.

23. The non-transitory machine readable storage medium of claim 17, wherein, when there is the conflict, a transition of a power domain in response to execution of the second power transaction is only visible to other transactions after the commit of the second power transaction is performed.

24. The non-transitory machine readable storage medium of claim 17, wherein the method further comprises performing a commit of a first thread and a second thread after concurrent execution of the first thread and the second thread on the hardware processor unless the first thread and the second thread are to modify a same memory address.