PROCESSOR AND PLATFORM ASSISTED NVDIMM SOLUTION USING STANDARD DRAM AND CONSOLIDATED STORAGE

• US 20160378344A1
• Filed: 06/24/2015
• Published: 12/29/2016
• Est. Priority Date: 06/24/2015
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nachimuthu, Murugasamy K., Kumar, Mohan J., Vergis, George
• Application Number:
  US14/748,798
• Publication Number:
  US 20160378344A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus for effecting a processor- and platform-assisted NVDIMM solution using standard DRAM and consolidated storage. The methods and apparatus enable selected data in DRAM devices, such as DIMMs to be automatically copied to a persistent storage device such as an SSD in response to detection of a power unavailable event or an operating system error or failure without any operating system intervention. In one aspect, a platform includes a power supply and a temporary power source, such as a capacitor-based energy storage device, a small battery, or a combination of the two, either integrated in the power supply or separate. When power becomes unavailable, the temporary power source is use to continue to provide power to selected components in one or more power protected domains. The energy stored in the temporary power source is sufficient to temporarily power the components to enable DRAM data to be written to the persistent storage device. Upon system restart, the previously-stored DRAM data is restored to one or more DRAM devices from which the data was originally copied.

Claims

1. A method for saving data in dynamic random access memory (DRAM) in a computer platform to a persistent storage device, wherein the computer platform includes a primary power source used to provide power to components in the computer platform during normal operation, the computer platform including the persistent storage device and running an operating system during normal operation, the method comprising:

detecting a power unavailable condition under which power is no longer being supplied by the primary power source to the computer platform; and

, in response to detection of the power unavailable condition,

automatically copying data in the DRAM to the persistent storage device without operating system intervention.

2. The method of claim 1, wherein the computer platform includes a processor including a plurality of caches, the method further comprising flushing data in the caches to DRAM prior to copying the data in the DRAM to the persistent storage device.

3. The method of claim 1, further comprising:

defining at least one region of the DRAM address space to comprise persistent DRAM;

configuring a persistent storage area on the persistent storage device in which the data in the persistent DRAM is to be stored; and

storing the data copied from the persistent DRAM to the persistent storage area.

4. The method of claim 1, wherein the computer platform includes a power protected direct memory access (DMA) engine, the method further comprising programming the power protected DMA engine to copy data in the DRAM to the persistent storage device.

5. The method of claim 1, wherein the computer platform further comprises:

a processor including,

at least one memory controller including a first memory controller; and

an input-output (IO) interface including a Direct Memory Access (DMA) engine;

at least one DRAM device in which data to be saved is stored prior to the power unavailable condition, operatively coupled to the first memory controller via a first memory controller-to-DRAM device link; and

an IO link coupling the persistent storage device to the IO interface,

wherein the method further comprises providing temporary power to a plurality of power protected components in the computer platform in response to detection of the power unavailable condition, wherein the plurality of power protected components include the first memory controller, the DMA engine, the at least one DRAM device, the first memory controller-to-DRAM device link, the IO link coupling the persistent storage device to the IO interface, and the persistent storage device.

6. The method of claim 5, wherein the temporary power is provided via a capacitor-based power circuit.

7. The method of claim 1, further comprising:

determining, during a platform initialization operation, whether the persistent storage device is storing any DRAM data that was previously copied from DRAM to the persistent storage device in response to a power unavailable condition; and

restoring the DRAM data to one or more DRAM devices from which the DRAM data was copied.

8. The method of claim 7, wherein the DRAM data is stored in a scrambled format before being copied to the persistent storage device, and the DRAM data is restored using a non-scrambled format.

9. The method of claim 1, wherein automatically copying data in the DRAM to the persistent storage device without operating system intervention is implemented through the use of a System Management Interrupt (SMI) and one or more System Management Mode (SMM) handlers, wherein in response to detection of the power unavailable condition an SMI is invoked that dispatches the one or more SMM handlers to service the SMI by copying the DRAM data to the persistent storage device.

10. A computing platform having a primary power source, comprising:

a processor including,

at least one memory controller including a first memory controller; and

an input-output (IO) interface including a Direct Memory Access (DMA) engine;

at least one dynamic random access memory (DRAM) device including a first DRAM device, operatively coupled to the first memory controller via a first memory controller-to-DRAM device link;

a persistent storage device, operatively coupled to the IO interface via an IO link; and

a temporary power source, operatively coupled to each of the first memory controller, the persistent storage device, the IO link, the first DRAM device, and the first memory controller-to-DRAM device link, wherein the temporary power source is configured to supply power to each of the first memory controller, the persistent storage device, the IO link, the first DRAM device, and the first memory controller-to-DRAM device link for a finite period of time in the event of a condition under which the primary power source no longer supplies power to the computer platform;

wherein the computer platform is configured to detect a condition under which the primary power source no longer supplies power to the computer platform and wherein in response to detection of the condition the IO interface is configured to copy data stored in the first DRAM to the persistent storage device via the DMA engine.

11. The computer platform of claim 10, wherein the compute platform is further configured to restore data that has previously been copied from the first DRAM device to the persistent storage device during a platform initialization operation performed by copying data from the persistent storage device to the first DRAM device via the DMA engine.

12. The compute platform of claim 10, wherein the compute platform includes a plurality of DRAM devices comprising DRAM dual in-line memory modules (DIMMs), each coupled to a memory controller via a memory controller-to-DRAM DIMM link, wherein the temporary power source is configured to supply power to each of the plurality of DRAM DIMMs, each memory controller, and each memory controller-to-DRAM DIMM link in the event of a condition under which the primary power source no longer supplies power to the computer platform;

and wherein in response to detection of the condition under which the primary power source no longer supplies power to the computer platform the IO interface is configured to copy data stored on each of the plurality of DRAM DIMMs to the persistent storage device via the DMA engine.

13. The compute platform of claim 12, wherein the processor includes at least two memory controllers, each memory controller coupled to at least two DRAM DIMMs.

14. The computer platform of claim 12, wherein the compute platform is further configured to restore data that has previously been copied from each of the plurality of DRAM DIMMS to the persistent storage device during a platform initialization operation performed by copying the previously copied data from the persistent storage device to each of the DRAM DIMMs via the DMA engine, wherein, upon restoration of the data each DRAM DIMM stores the same data that it was storing prior to the occurrence of the condition under which the primary power source no longer was supplying power to the computer platform.

15. The computer platform of claim 10, wherein the IO link comprises a Peripheral Control Interconnect Express (PCIe) link.

16. The computer platform of claim 10, wherein the persistent storage device comprises a solid-state drive (SSD).

17. The computer platform of claim 10, wherein the processor includes at least one processor cache, and manages a write-pending queue, and wherein in response to detection of the unavailable power condition, data in the at least one processor cache and the write-pending queue is flushed to the first DRAM device prior to copying the data from the first DRAM device to the persistent storage device.

18. The computer platform of claim 10, wherein the processor includes a central processor unit (CPU) with a plurality of cores, and the IO interface is coupled to a plurality of IO links, and wherein in response to detect of the unavailable power condition the processor enters a power down state where all of the IO links except the power protected links have their power reduced, and the cores are operated in a reduced power state.

19. The computer platform of claim 10, wherein upon completion of copying the data from the DRAM device to the persistent storage device, meta-data stored in the persistent storage device is updated to indicate the data has been successfully saved to the persistent storage device.

20. A processor, configured to be installed in a computer platform including a power supply having a primary power input source, one or more dynamic random access memory (DRAM) devices, and a persistent storage device, the processor comprising:

a plurality of processor cores, operatively coupled to an interconnect;

at least one memory controller including a first memory controller and memory controller interface, operatively coupled to the interconnect and configured to interface with a first memory controller to DRAM device link coupled at an opposing end to a first DRAM device when the processor is installed in the computer platform;

an input-output (IO) interface, operatively coupled to the interconnect and including a link interface for an IO link to which the persistent storage device is coupled;

a Direct Memory Access (DMA) engine; and

logic, configured upon operation of the processor to,

detect a power unavailable condition under which the primary power input source no longer supplies power to the power supply; and

in response to detection of the condition,

copy DRAM data stored in the first DRAM device to the persistent storage device.

21. The processor of claim 20, further comprising a Direct Memory Access (DMA) engine, and wherein the DRAM data stored in the first DRAM device is copied to the persistent storage device via the DMA engine.

22. The processor of claim 20, wherein the processor is configured to implement a System Management Interrupt (SMI) and to operate in a System Management Mode (SMM), and further wherein the processor is configured, upon operation and in response to the power unavailable condition, to invoke an SMI and dispatch one or more SMM handlers to service the SMI by copying the DRAM data stored in the first DRAM device to the persistent storage device.

23. The processor of claim 20, wherein the processor further comprises at least one of a APIC (Advance Programmable Interrupt Controller) logic block and a power control unit (PCU), and in response to the detection of the condition at least one of the APIC logic block and the PCU is configured to provide power to selected components in the processor to enable the DRAM data to be copied to the persistent storage device, while reducing power to other components on the processor that are not employed to facilitate transfer of data to the persistent storage device via the DRAM data copy.

24. The processor of claim 20, wherein the compute platform comprises a multi-socket platform having a plurality of sockets and including a first socket comprising a local socket and a second socket comprising a remote socket and a socket-to-socket interconnect between the first and second sockets, wherein the processor is configured to have respective instances of the processor installed in respective local and remote sockets, and wherein the processor further comprises a socket-to-socket interconnect interface configured to couple to the socket-to-socket interconnect, and further wherein the processor includes logic configured, in response to detection of the power unavailable condition and when the processor is installed in a local socket, to:

copy data from one or more DRAM devices accessed via one or more memory controllers on the processor to the persistent storage device; and

interface with the processor in the remote socket to copy data from one or more DRAM devices accessed via one or more memory controllers on the processor installed in the remote socket to the persistent storage device.

25. The processor of claim 20, wherein upon completion of copying the data from the first DRAM device to the persistent storage device, the processor is configured to send data over the IO link to update meta-data stored in the persistent storage device to indicate the data has been successfully saved to the persistent storage device.