ALIGNING MEMORY ACCESS OPERATIONS TO A GEOMETRY OF A STORAGE DEVICE

• US 20160378356A1
• Filed: 06/23/2015
• Published: 12/29/2016
• Est. Priority Date: 06/23/2015
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: COLGROVE, JOHN, KIRKPATRICK, PETER E.
• Granted Patent: US 10,310,740 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Aligning memory access operations to a geometry of a storage device, including: receiving, by a storage array controller, information describing the layout of memory in the storage device; determining, by the storage array controller, a write size in dependence upon the layout of memory in the storage device; and sending, by the storage array controller, a write request addressed to a location within the memory unit in dependence upon the layout of memory in the storage device.

Claims

1. A method of aligning memory access operations to a geometry of a single storage device, the method comprising:

receiving, by a storage array controller, information describing the layout of memory in the single storage device;

determining, by the storage array controller and in dependence upon the layout of memory in the single storage device, a write size and a physical address; and

sending, by the storage array controller, a write request specifying the write size and addressed to the physical address within the single storage device.

2. The method of claim 1 further comprising sending, by the storage array controller, a request to expose an underlying physical layout of the memory in the storage device.

3. The method of claim 1 wherein the information describing the layout of memory in the storage device includes information describing a size of a writeable memory unit in the storage device, and wherein the storage array controller, in dependence upon the storage array controller determining the physical address, relieves the single storage device from translating a logical address for the write request into the physical address.

4. The method of claim 1 wherein the information describing the layout of memory in the storage device includes information describing a size of an erasable memory unit in the storage device.

5. The method of claim 1 wherein sending, by the storage array controller, a write request addressed to a location within the memory unit in dependence upon the layout of memory in the storage device further comprises:

identifying an unused portion of the memory unit; and

including an address for the unused portion of the memory unit in the write request.

6. The method of claim 1 wherein sending, by the storage array controller, a write addressed to a location within the memory unit in dependence upon the layout of memory in the storage device further comprises:

identifying an unused memory unit; and

including an address for the unused memory unit in the write request.

7. A storage array controller for aligning memory access operations to a geometry of a single storage device, the storage array controller comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the storage array controller to carry out the steps of:

receiving information describing the layout of memory in the single storage device;

determining, in dependence upon the layout of memory in the single storage device, a write size and a physical address; and

sending a write request specifying the write size and addressed to the physical address within the single storage device.

8. The storage array controller of claim 7 further comprising computer program instructions that, when executed by the computer processor, cause the storage array controller to carry out the step of sending a request to expose an underlying physical layout of the memory in the storage device.

9. The storage array controller of claim 7 wherein the information describing the layout of memory in the storage device includes information describing a size of a writeable memory unit in the storage device.

10. The storage array controller of claim 7 wherein the information describing the layout of memory in the storage device includes information describing a size of an erasable memory unit in the storage device.

11. The storage array controller of claim 7 wherein sending a write request addressed to a location within the memory unit in dependence upon the layout of memory in the storage device further comprises:

identifying an unused portion of the memory unit; and

including an address for the unused portion of the memory unit in the write request.

12. The storage array controller of claim 7 wherein sending, by the storage array controller, a write addressed to a location within the memory unit in dependence upon the layout of memory in the storage device further comprises:

identifying an unused memory unit; and

including an address for the unused memory unit in the write request.

13. A computer program product for aligning memory access operations to a geometry of a single storage device, the computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:

receiving, by a storage array controller, information describing the layout of memory in the single storage device;

determining, by the storage array controller and in dependence upon the layout of memory in the single storage device, a write size and a physical address; and

sending, by the storage array controller, a write request specifying the write size and addressed to the physical address within the single storage device.

14. The computer program product of claim 13 further comprising sending, by the storage array controller, a request to expose an underlying physical layout of the memory in the storage device.

15. The computer program product of claim 13 wherein the information describing the layout of memory in the storage device includes information describing a size of a writeable memory unit in the storage device.

16. The computer program product of claim 13 wherein the information describing the layout of memory in the storage device includes information describing a size of an erasable memory unit in the storage device.

17. The computer program product of claim 13 wherein sending, by the storage array controller, a write request addressed to a location within the memory unit in dependence upon the layout of memory in the storage device further comprises:

identifying an unused portion of the memory unit; and

including an address for the unused portion of the memory unit in the write request.

18. The computer program product of claim 13 wherein sending, by the storage array controller, a write addressed to a location within the memory unit in dependence upon the layout of memory in the storage device further comprises:

identifying an unused memory unit; and

including an address for the unused memory unit in the write request.