CACHE MEMORY AND PROCESSOR SYSTEM

• US 20160378592A1
• Filed: 09/12/2016
• Published: 12/29/2016
• Est. Priority Date: 03/20/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: IKEGAMI, Kazutaka, Fujita, Shinobu, Noguchi, Hiroki
• Granted Patent: US 10,642,685 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 12/16 Protection against loss of memory contents contains no material, see G06F11/00
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/221 Static RAM
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/225 Hybrid cache memory, e.g. having both volatile and non-volatile portions
• CPC Class Codes: G06F 2212/403 Error protection encoding, e.g. using parity or ECC codes
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/068 Hybrid storage device

Abstract

A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry, and a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code.

Claims

1. A cache memory comprising:

cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry;

a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry; and

a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code.

2. The cache memory according to claim 1,

wherein the cache memory circuitry stores tag information for access to the data which is stored or is to be stored in the lower-level memory, and

wherein the first redundancy code storage and the second redundancy code storage are capable of storing a redundancy code of the data stored in the cache memory circuitry and a redundancy code of the tag information corresponding to the data stored in the cache memory circuitry.

3. The cache memory according to claim 1,

wherein the second redundancy code storage is used for storing and reading the redundancy code during an operation of a processor core, and

wherein the first redundancy code storage stores the redundancy code stored in the second redundancy code storage after the processor core stops the operation.

4. The cache memory according to claim 3, wherein the second redundancy code storage stores the redundancy code stored in the first redundancy code storage when the processor core restarts the operation.

5. The cache memory according to claim 4, wherein the second redundancy code storage stores updatability information as to whether or not the redundancy code stored in the first redundancy code storage is to be stored when the processor core restarts the operation.

6. The cache memory according to claim 1, further comprising a first storage which stores the redundancy code to be stored in the first redundancy code storage before the redundancy code is stored in the first redundancy code storage,

wherein the first storage and the second redundancy code storage store the redundancy code in a parallel manner,

wherein the first redundancy code storage stores the redundancy code when the first storage does not perform a write operation, and

wherein the first redundancy code storage stores the redundancy code which is stored in the first storage and is not yet stored in the first redundancy code storage when the processor core stops the operation.

7. The cache memory according to claim 1, further comprising a redundancy code flow controller which controls reading and writing of the redundancy code in the first redundancy code storage and the second redundancy code storage according to a state of the operation of the processor core.

16. The cache memory according to claim 1, wherein the nonvolatile memory cell is a magnetoresistive RAM (MRAM) cell.

8. A processor system comprising:

a processor core; and

a cache memory,

the cache memory comprises;

cache memory circuitry comprising a nonvolatile memory cell storing at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry;

a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry; and

a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code.

9. The processor system according to claim 8,

wherein the cache memory circuitry stores tag information necessary for access to the data in addition to the data which is stored or is to be stored in the lower-level memory, and

wherein the first redundancy code storage and the second redundancy code storage are capable of storing a redundancy code of the data stored in the cache memory circuitry and a redundancy code of the tag information corresponding to the data stored in the cache memory circuitry.

10. The processor system according to claim 8, wherein the cache memory further includes a redundancy code flow controller which controls reading and writing of the redundancy code in the first redundancy code storage and the second redundancy code storage according to a state of the operation of the processor core.

11. The processor system according to claim 10, wherein the redundancy code flow controller performs control of storing the redundancy code in the second redundancy code storage, during the operation of the processor core.

12. The processor system according to claim 10, wherein the redundancy code flow controller performs control of copying the redundancy code stored in the second redundancy code storage to the first redundancy code storage when the processor core stops the operation.

13. The processor system according to claim 10, wherein the redundancy code flow controller performs control of copying the redundancy code stored in the first redundancy code storage to the second redundancy code storage when the processor core restarts the operation.

14. The processor system according to claim 10, further comprising a first storage which stores the redundancy code to be stored in the first redundancy code storage before the redundancy code is stored in the first redundancy code storage,

wherein the first redundancy code storage stores the redundancy code when the first storage does not perform a write operation, and

wherein the redundancy code flow controller performs control of storing the redundancy code in the first storage and the second redundancy code storage in a parallel manner during the operation of the processor core and performs control of storing the redundancy code which is stored in the first storage and is not yet stored in first redundancy code storage when the processor core stops the operation.

15. The processor system according to claim 8, further comprising:

a first semiconductor chip on which the cache memory circuitry and the first redundancy code storage are provided; and

a second semiconductor chip on which the processor core and the second redundancy code storage are provided, the second semiconductor chip being stacked with the first semiconductor chip.

17. The processor system according to claim 8, wherein the nonvolatile memory cell is a magnetoresistive RAM (MRAM) cell.