VARIABLE CHANGE MEMORY AND THE WRITING METHOD OF THE SAME

• US 20160379697A1
• Filed: 09/09/2016
• Published: 12/29/2016
• Est. Priority Date: 03/13/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: FUJITA, Katsuyuki, SAKAI, Shintaro, NAKAYAMA, Masahiko, NORO, Hiromi
• Granted Patent: US 9,858,973 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.

Claims

1. A variable change memory comprising:

a bit line extending in a first direction;

a word line extending in a second direction crossing the first direction;

a memory cell array including a plurality of blocks each including memory cells, the memory cells each including a select transistor and a variable resistive element which stores different data depending on a change in a resistance value, the variable resistive element having one end connected to the bit line and the other end connected to a drain of the select transistor, and the select transistor having the drain, a source connected to a source line and a gate connected to the word line;

a resonance line connected to the bit line and arranged to be substantially symmetrical in the memory cell array;

a clock generator arranged in the memory cell array so that the blocks and the resonance line is arranged to be substantially symmetrical and which applies a voltage which oscillates at a predetermined period to the resonance line; and

a write driver which supplies a write current to the bit line,

wherein the voltage which oscillates at the predetermined period and the write current are supplied to the bit line.

2. The variable change memory according to claim 1, further comprising:

a controller which controls timings of supplying the voltage which oscillates at the predetermined period and the write current to the bit line,

the controller supplying the voltage which oscillates at the predetermined period to the bit line via the resonance line and then supplying the write current to the bit line.

3. The variable change memory according to claim 2, wherein the controller supplies a combined wave obtained by superimposing the voltage which oscillates at the predetermined period and the write current to the bit line.

4. The variable change memory according to claim 3, wherein the controller executes a write operation for the variable resistive element a plurality of times, and

the controller supplies the combined wave to the bit line in each write operation.

5. The variable change memory according to claim 4, further comprising a diode;

the diode capable of supplying the voltage which oscillates at the predetermined period from the resonance line to the bit line.

6. The variable change memory according to claim 5, further comprising:

a semiconductor substrate;

the select transistor disposed on an active region in a surface of the semiconductor substrate;

a first contact plug having a bottom surface connected to the drain of the select transistor and an upper surface connected to the bit line, the bit line being arranged in the first direction;

the diode comprised by sequentially stacking, on the bit line, a first stacked film in which a first carrier density is implanted and a second stacked film in which a second carrier density is implanted;

the resonance line having the bottom surface connected to the upper surface of the diode and arranged in the second direction perpendicular to the first direction; and

the source line having the bottom surface connected to the source of the transistor, located above the resonance line via the variable resistive element, and arranged in the first direction.

7. The variable change memory according to claim 5, further comprising:

a sense amplifier which reads the resistance value of the variable resistive element and recognizes a magnetization direction,

wherein upon determining as a result of the read which the magnetization direction of the variable resistive element is different from the write data, the controller supplies the voltage which oscillates at the predetermined period and the write current to the bit line and the resonance line and executes the write.

8. A variable change memory comprising:

a memory cell array including a plurality of blocks arranged to be bilaterally and vertically symmetrical to each other, each block including a plurality of memory cells arranged along rows and columns;

a clock generator arranged at a center of the memory cell array;

first resonance lines arranged in correspondence with the blocks vertically along a first direction with respect to the clock generator as the center, each first resonance line including a first buffer at a first output end;

second resonance lines arranged in correspondence with the blocks horizontally along a second direction perpendicular to the first direction, each second resonance line having a first input end connected to the first output end and including a second buffer at a second output end;

third resonance lines arranged in correspondence with a half of a length of the blocks vertically along the first direction, each third resonance line having a second input end connected to the second output end and including a third buffer at a third output end; and

fourth resonance lines each extending across the memory cell array so as to be connected to an output end of the third buffer and connected, via a diode, to a bit line arranged in the first direction.

9. The variable change memory according to claim 8, further comprising a write driver arranged for the plurality of blocks,

wherein the clock generator supplies a voltage which oscillates at a predetermined period to the bit line via the first resonance line, the second resonance line, the third resonance line, and the fourth resonance line, and

the write driver supplies a write current to the bit line.

10. The variable change memory according to claim 9, further comprising a controller which controls timings of supplying the voltage which oscillates at the predetermined period, and the write current to the bit line,

the controller supplying the voltage that oscillates at the predetermined period to the bit line and then supplying the write current to the bit line.

11. The variable change memory according to claim 10, wherein the controller supplies a combined wave obtained by superimposing the voltage which oscillates at the predetermined period and the write current to the bit line.

12. The variable change memory according to claim 11, wherein the controller executes a write operation for the variable resistive element a plurality of times, and

the controller supplies the combined wave to the bit line in each write operation.

13. A writing method of a memory having a memory cell including an MTJ element, comprising:

applying a voltage which oscillates at a predetermined period to the MTJ element; and

applying, to the MTJ element, a predetermined voltage higher than a peak voltage of the voltage which oscillates at the predetermined period after the voltage which oscillates at the predetermined period is applied to the MTJ element.

14. The writing method of the memory according to claim 13, wherein one end of the MTJ element is connected to a bit line,

the other end of the MTJ element is connected to one end of a select transistor,

the other end of the select transistor is connected to a source line, and

the voltage which oscillates at the predetermined period and the predetermined voltage are applied from a side of the bit line to the MTJ element.

15. The writing method of the memory according to claim 13, wherein the predetermined period is not less than 1 GHz.

16. The writing method of the memory according to claim 13, wherein the predetermined period is not less than 10 GHz.

17. The writing method of the memory according to claim 13, wherein an application time of the voltage which oscillates at the predetermined period is shorter than the application time of the predetermined voltage.

18. The writing method of the memory according to claim 17, wherein the voltage that oscillates at the predetermined period is superimposed on the predetermined voltage at a start of application of the predetermined voltage.