SEMICONDUCTOR MEMORY DEVICE

• US 20160379699A1
• Filed: 09/09/2016
• Published: 12/29/2016
• Est. Priority Date: 03/11/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: TAKAHASHI, Masahiro, INABA, Tsuneo
• Granted Patent: US 9,728,239 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/067 Single-ended amplifiers

Abstract

According to one embodiment, a semiconductor memory device includes a first memory cell array including a first memory cell having a variable resistive element, a second memory cell array including a second memory cell having the variable resistive element, a reference signal generation circuit which generates a reference signal, a sense amplifier having a first input terminal and a second input terminal, and a read enable control circuit which generates a read enable signal in accordance with a command from outside and control switching between a single cell read mode and a twin cell read mode.

Claims

1. A semiconductor memory device comprising:

a first memory cell array including a first memory cell having a variable resistive element;

a second memory cell array including a second memory cell having the variable resistive element;

a reference signal generation circuit which generates a reference signal;

a sense amplifier having a first input terminal and a second input terminal; and

a read enable control circuit which generates a read enable signal in accordance with a command from outside and control switching between a single cell read mode and a twin cell read mode.

2. The device of claim 1, further comprising:

a first series-connected element which includes a first switching element and electrically connects the first memory cell array and the first input terminal of the sense amplifier;

a second series-connected element which includes a second switching element and electrically connects the second memory cell array and the first input terminal of the sense amplifier;

a third series-connected element which includes a third switching element and electrically connects the second memory cell array and the second input terminal of the sense amplifier; and

a fourth series-connected element which includes a fourth switching element and electrically connects the reference signal generation circuit and the second input terminal of the sense amplifier.

3. The device of claim 2, wherein the read enable control circuit renders the first series-connected element and the fourth series-connected element conductive, thereby reading data of the first memory cell.

4. The device of claim 2, wherein the read enable control circuit renders the second series-connected element and the fourth series-connected element conductive, thereby reading data of the second memory cell.

5. The device of claim 2, wherein the read enable control circuit renders the first series-connected element and the third series-connected element conductive, thereby reading data of the first memory cell.

6. The device of claim 5, wherein the second memory cell stores complementary data of the first memory cell.

7. The device of claim 2, wherein

the first switching element includes a first transistor having a gate to which a first read enable signal of “

H”

level or “

L”

level is supplied, and a second transistor having a gate to which a first signal of “

M”

level is supplied,

the second switching element includes a third transistor having a gate to which a second read enable signal of “

H”

level or “

L”

level is supplied, and a fourth transistor having a gate to which the first signal is supplied,

the third switching element includes a fifth transistor having a gate to which a third read enable signal of “

H”

level or “

L”

level is supplied, and a sixth transistor having a gate to which the first signal is supplied, and

the fourth switching element includes a seventh transistor having a gate to which a fourth read enable signal of “

H”

level or “

L”

level is supplied, and an eighth transistor having a gate to which a second signal of “

M”

level is supplied.

8. The device of claim 7, wherein an interconnection which supplies the third read enable signal is adjacent to an interconnection which supplies the first signal and/or an interconnection which supplies the second signal.

9. The device of claim 7, wherein the read enable control circuit includes:

a first NAND circuit which receives a third signal and output an operation result;

a first inverter circuit which receives a signal output from the first NAND circuit, invert the signal, and output the first read enable signal;

a second NAND circuit which receives an inverted signal of the third signal and output an operation result;

a second inverter circuit which receives a signal output from the second NAND circuit, invert the signal, and output the second read enable signal;

a third NAND circuit which receives a fourth signal and output an operation result;

a third inverter circuit which receives a signal output from the third NAND circuit, invert the signal, and output the third read enable signal;

a fourth NAND circuit which receives an inverted signal of the fourth signal and output an operation result; and

a fourth inverter circuit which receives a signal output from the fourth NAND circuit, invert the signal, and output the fourth read enable signal.

10. The device of claim 2, further comprising:

a fifth series-connected element which includes a fifth switching element and electrically connects the first memory cell array and a first ground potential terminal; and

a sixth series-connected element which includes a sixth switching element and electrically connects the reference signal generation circuit and a second ground potential terminal.

11. The device of claim 10, wherein

the fifth switching element includes a ninth transistor having a gate to which the first signal is supplied, and a 10th transistor having a gate to which a third signal of “

L”

level is supplied, and

the sixth switching element includes a 11th transistor having a gate to which the second signal is supplied, and a 12th transistor having a gate to which the third signal is supplied.

12. The device of claim 1, wherein the read enable control circuit further comprises a read enable control circuit which generates the read enable signal based on an address signal input by the command from outside and control switching between the single cell read mode and the twin cell read mode.

13. A semiconductor memory device comprising:

a first memory cell array including a first memory cell having a variable resistive element;

a second memory cell array including a second memory cell having the variable resistive element;

a reference signal generation circuit which generates a reference signal;

a sense amplifier having a first input terminal and a second input terminal; and

a control circuit which controls switching between a single cell read mode and a twin cell read mode in accordance with a command from outside.

14. The device of claim 13, further comprising:

a first series-connected element which includes a first switching element and electrically connects the first memory cell array and the first input terminal of the sense amplifier;

a second series-connected element which includes a second switching element and electrically connects the second memory cell array and the first input terminal of the sense amplifier;

a third series-connected element which includes a third switching element and electrically connects the second memory cell array and the second input terminal of the sense amplifier; and

a fourth series-connected element which includes a fourth switching element and electrically connects the reference signal generation circuit and the second input terminal of the sense amplifier.

15. The device of claim 14, wherein the control circuit renders the first series-connected element and the fourth series-connected element conductive, thereby reading data of the first memory cell.

16. The device of claim 14, wherein the control circuit renders the second series-connected element and the fourth series-connected element conductive, thereby reading data of the second memory cell.

17. The device of claim 14, wherein the control circuit renders the first series-connected element and the third series-connected element conductive, thereby reading data of the first memory cell.

18. The device of claim 17, wherein the second memory cell stores complementary data of the first memory cell.

19. The device of claim 14, wherein

the first switching element includes a first transistor having a gate to which a read enable signal of “

H”

level is supplied, and a second transistor having a gate to which a first analog signal of “

M”

level or “

L”

level is supplied,

the second switching element includes a third transistor having a gate to which the read enable signal is supplied, and a fourth transistor having a gate to which a second analog signal of “

M”

level or “

L”

level is supplied,

the third switching element includes a fifth transistor having a gate to which the read enable signal is supplied, and a sixth transistor having a gate to which a third analog signal of “

M”

level or “

L”

level is supplied, and

the fourth switching element includes a seventh transistor having a gate to which the read enable signal is supplied, and an eighth transistor having a gate to which a fourth analog signal of “

M”

level or “

L”

level is supplied.

20. The device of claim 13, wherein the control circuit further comprises a read enable control circuit which generates an analog signal based on an address signal input by the command from outside and control switching between the single cell read mode and the twin cell read mode.