MEMORY DEVICE

• US 20160379708A1
• Filed: 09/06/2016
• Published: 12/29/2016
• Est. Priority Date: 03/07/2014
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KATAYAMA, Akira
• Granted Patent: US 9,953,707 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

According to one embodiment, a memory device includes a sense amplifier including a first input node and a second input node, a first path including a memory cell to be selectively connected to the first input node, and a second path including a reference cell to be selectively connected to the second input node, and is configured to change an input value at the second input node in accordance with the state of the memory cell.

Claims

1. A memory device comprising:

a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node;

a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and

a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node,

wherein the input value at the second input node of the sense amplifier is changed such that a change amount of the input value between two different temperatures T2 and (T2+Δ

T) in a second temperature region, at a temperature higher than in a first temperature region, of the memory cell becomes larger than the change amount of the input value between two different temperatures T1 and (T1+Δ

T) in the first temperature region of the memory cell,

where Δ

T is an increase amount of the temperature.

2. The memory device according to claim 1, wherein the change amount of the input value at the second input node is proportional to a leak current in the first path and has a proportionality constant smaller than 1.

3. The memory device according to claim 1, wherein a reference current generation circuit provided with a replica circuit is connected to the second input node of the sense amplifier.

4. The memory device according to claim 3, wherein the replica circuit comprises a leak monitor circuit configured to monitor a leak current in the first path.

5. The memory device according to claim 4, wherein the leak monitor circuit comprises a replica of the memory cell.

6. The memory device according to claim 4, wherein the leak monitor circuit comprises a replica of a local column switch configured to select or unselect the memory cell.

7. The memory device according to claim 1, wherein a current generation circuit provided with a replica circuit is connected to the first input node of the sense amplifier.

8. The memory device according to claim 1, wherein the memory cell comprises a resistance change memory element as a memory element.

9. The memory device according to claim 1, wherein the memory cell comprises a magnetoresistive element as a memory element.

10. A memory device comprising:

a sense amplifier including a first input node and a second input node and configured to output a signal based on a difference between input values at the first input node and the second input node;

a first path including a memory cell to be selectively connected to the first input node and provided between the first input node and a ground node; and

a second path including a reference cell to be selectively connected to the second input node and provided between the second input node and the ground node,

wherein a reference current generation circuit provided with a replica circuit is connected to the second input node of the sense amplifier.

11. The memory device according to claim 10, wherein the replica circuit generates a current that is proportional to a leak current in the first path and has a proportionality constant smaller than 1.

12. The memory device according to claim 10, wherein the replica circuit comprises a leak monitor circuit configured to monitor a leak current in the first path.

13. The memory device according to claim 12, wherein the leak monitor circuit comprises a replica of the memory cell.

14. The memory device according to claim 12, wherein the leak monitor circuit comprises a replica of a local column switch configured to select or unselect the memory cell.

15. The memory device according to claim 10, wherein a current generation circuit provided with a replica circuit is connected to the first input node of the sense amplifier.

16. The memory device according to claim 15, wherein the replica circuit provided in the current generation circuit comprises a leak monitor circuit configured to monitor a leak current in the first path.

17. The memory device according to claim 15, wherein the replica circuit provided in the current generation circuit comprises a replica of the memory cell.

18. The memory device according to claim 15, wherein the replica circuit provided in the current generation circuit comprises a replica of a local column switch configured to select or unselect the memory cell.

19. The memory device according to claim 10, wherein the memory cell comprises a resistance change memory element as a memory element.

20. The memory device according to claim 10, wherein the memory cell comprises a magnetoresistive element as a memory element.