SEMICONDUCTOR POWER DEVICE AND METHOD FOR PRODUCING SAME

• US 20160379825A1
• Filed: 09/07/2016
• Published: 12/29/2016
• Est. Priority Date: 02/02/2011
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: NAKANO, Yuki
• Granted Patent: US 9,947,536 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02241 III-V semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/044 Conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66045 : Field-effect transistors
• CPC Class Codes: H01L 29/6606 : the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66068 : the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66446 : with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8611 : Planar PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Claims

1. A method for producing a semiconductor power device, the semiconductor power device having a semiconductor layer and a trench-gate type transistor structure formed in the semiconductor layer, the trench-gate type transistor structure comprising:

a first conductivity type source region;

a second conductivity type body region contiguous to the source region;

a first conductivity type drift region contiguous to the body region;

a gate trench formed in such a way as to straddle the source region, the body region, and the drift region;

a gate insulation film formed on an inner surface of the gate trench; and

a gate electrode facing the body region with the gate insulation film therebetween, the method comprising;

a step of forming the gate trench from a surface of the semiconductor layer toward an inside thereof;

a step of forming a first insulation film on the inner surface of the gate trench;

a step of removing a part on a bottom surface of the gate trench in the first insulation film; and

a step of forming a second insulation film having a dielectric constant higher than SiO₂ in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

2. The method for producing the semiconductor power device according to claim 1, wherein the step of forming the first insulation film is a step of forming the first insulation film according to a thermal oxidation method, and

the step of forming the second insulation film is a step of forming the second insulation film according to a CVD method.

3. The method for producing the semiconductor power device according to claim 1, wherein the first insulation film is made of SiO₂.

4. The method for producing the semiconductor power device according to claim 1, wherein the semiconductor layer is made of a wide bandgap semiconductor.

5. The method for producing the semiconductor power device according to claim 4, wherein the wide bandgap semiconductor includes SiC, GaN or diamond.

6. The method for producing the semiconductor power device according to claim 4, wherein the wide bandgap semiconductor includes SiC, and

the surface of the semiconductor layer is an Si (silicon) plane of SiC.

7. The method for producing the semiconductor power device according to claim 1, wherein the step of forming the first insulation film includes a step of forming the first insulation film having a first portion on a side surface of the gate trench and a second portion on the bottom surface of the gate trench which is thinner than the first portion.

8. The method for producing the semiconductor power device according to claim 1, wherein the step of removing the first insulation film includes a step of selectively removing a portion of the first insulation film on corner portions of both ends of the gate trench.

9. The method for producing the semiconductor power device according to claim 1, wherein the step of removing the first insulation film includes a step of removing the first insulation film by etching.

10. The method for producing the semiconductor power device according to claim 1, wherein the second insulation film is made of a high-k dielectric material.

11. The method for producing the semiconductor power device according to claim 10, wherein the high-k dielectric material includes SiN, Al₂O₃ or AlON.

12. The method for producing the semiconductor power device according to claim 1, comprising a step of the gate insulation film having a two-layer structure consisting of the first insulation film and the second insulation film on a side surface of the gate trench and a single-layer structure consisting of the second insulation film on the bottom surface of the gate trench by forming the second insulation film.