STRUCTURE WITH EMEDDED EFS3 AND FINFET DEVICE

• US 20160379987A1
• Filed: 06/25/2015
• Published: 12/29/2016
• Est. Priority Date: 06/25/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Ming Chyi, Wu, Chang-Ming, Liu, Shih-Chang, Chang, Yu-Hsing, Tseng, Yuan-Tai
• Granted Patent: US 9,570,454 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

The present disclosure relates to an integrated chip having a FinFET device and an embedded flash memory device, and a method of formation. In some embodiments, the integrated chip has a logic region and a memory region that is laterally separated from the logic region. The logic region has a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate. A gate electrode is arranged over the first plurality of fins of semiconductor material. The memory region has a second plurality of fins of semiconductor material extending outward from the semiconductor substrate. An embedded flash memory cell is arranged onto the second plurality of fins of semiconductor material. The resulting integrated chip structure provides for good performance since it contains both a FinFET device and an embedded flash memory device.

Claims

1. An integrated chip, comprising:

a logic region comprising a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate and respectively comprising a first long edge and a first short edge;

a gate electrode straddling the first plurality of fins of semiconductor material;

an embedded flash memory region, laterally separated from the logic region along a first direction, and comprising a second plurality of fins of semiconductor material protruding outward from the semiconductor substrate and respectively comprising a second long edge and a second short edge, wherein the second short edge has a greater width than the first short edge; and

a plurality of embedded flash memory cells arranged onto the second plurality of fins of semiconductor material.

2. The integrated chip of claim 1, further comprising:

a dielectric material arranged over the semiconductor substrate at a position laterally between the first plurality of fins of semiconductor material and the second plurality of fins of semiconductor material.

3. The integrated chip of claim 2, wherein the plurality of embedded flash memory cells respectively comprise:

a floating gate disposed over one of the second plurality of fins of semiconductor material and laterally separated from an adjacent floating gate by the second plurality of fins in a first direction and by the dielectric material in a second direction;

a control gate vertically separated from the floating gate by a control gate dielectric;

a select gate arranged along a first side of the control gate and separated from the control gate and the floating gate by a sidewall dielectric layer; and

an erase gate arranged along a second side of the control gate and separated from the control gate and the floating gate by the sidewall dielectric layer.

4. The integrated chip of claim 3, further comprising:

a gate dielectric layer vertically arranged between the floating gate and the one of the second plurality of fins of semiconductor material.

5. The integrated chip of claim 3, wherein the floating gate has outermost sidewalls that are substantially aligned with outermost sidewalls of the one of the second plurality of fins of semiconductor material.

6. The integrated chip of claim 3, wherein the floating gate is vertically overlying and laterally offset from upper surfaces of the first plurality of fins of semiconductor material.

7. The integrated chip of claim 3, wherein the control gate extends in the first direction over more than one of the second plurality of fins of semiconductor material.

8. The integrated chip of claim 3, further comprising:

a hard mask layer arranged over the gate electrode and having an upper surface that is substantially aligned with an upper surface of the select gate.

9. The integrated chip of claim 3, wherein an upper surface of the gate electrode underlies an upper surface of the control gate.

10. The integrated chip of claim 1, wherein upper surfaces of the first plurality of fins of semiconductor material are vertically aligned with upper surfaces of the second plurality of fins of semiconductor material.

12. The integrated chip of claim 1, wherein the first plurality of fins of semiconductor material are arranged in the first direction at a first pitch and the second plurality of fins of semiconductor material are arranged in the first direction at a second pitch that is larger than the first pitch.

21. The integrated chip of claim 1, wherein the gate electrode extends over the plurality of first fins in a first direction that is perpendicular to a second direction of a long axis of the second plurality of fins of semiconductor material.

22. The integrated chip of claim 2, wherein the plurality of embedded flash memory cells respectively comprise a control gate dielectric layer having a lower surface contacting the dielectric material.

23. The integrated chip of claim 3, wherein the control gate has a bottom surface that is vertically above top surfaces of the second plurality of fins of semiconductor material.

11. (canceled)

13. An integrated chip, comprising

a first plurality of fins of semiconductor material protruding outward from a semiconductor substrate and laterally separated by a dielectric material overlying the semiconductor substrate;

a gate electrode arranged over and along sidewalls of the first plurality of fins of semiconductor material;

a second plurality of fins of semiconductor material extending outward from the semiconductor substrate, and laterally separated from the first plurality of fins of semiconductor material in a first direction by the dielectric material;

a plurality of floating gates vertically separated from the second plurality of fins of semiconductor material by a gate dielectric layer and laterally separated from one another by the dielectric material;

a control gate vertically separated from the plurality of floating gates and the dielectric material by a control gate dielectric;

a select gate separated from a first side of the control gate, along a second direction perpendicular to the first direction, by a sidewall dielectric layer; and

an erase gate separated from a second side of the control gate along the second direction by the sidewall dielectric layer.

14. The integrated chip of claim 13, wherein the plurality of floating gates have sidewalls that are substantially aligned with sidewalls of the second plurality of fins of semiconductor material.

15. The integrated chip of claim 13, wherein the control gate extends in the first direction over more than one of the second plurality of fins of semiconductor material.

16. The integrated chip of claim 13, wherein the first plurality of fins of semiconductor material have a first width in the first direction and the second plurality of fins of semiconductor material have a second width in the first direction that is larger than the first width.

18. The integrated chip of claim 13, wherein upper surfaces of the first plurality of fins of semiconductor material are substantially aligned with upper surfaces of the second plurality of fins of semiconductor material.

17. (canceled)

19. A method of forming an integrated chip, comprising:

patterning a semiconductor substrate to concurrently form a first plurality of fins of semiconductor material that protrude from the semiconductor substrate and a second plurality of fins of semiconductor material that protrude from the semiconductor substrate, wherein the first plurality of fins of semiconductor material are laterally separated from the second plurality of fins of semiconductor material;

forming a dielectric material laterally separating the first plurality of fins and the second plurality of fins;

forming a gate dielectric layer and a floating gate layer over the second plurality of fins within recesses in the dielectric material;

forming a control gate dielectric over the dielectric material and the floating gate layer;

forming a control gate over the control gate dielectric;

selectively etching the dielectric material to form a cavity extending over and along sidewalls of the first plurality of fins; and

depositing a conductive material that forms a gate electrode within the cavity and an erase gate and a select gate over the second plurality of fins.

20. (canceled)