ARRAY SUBSTRATE, PREPARATION METHOD THEREOF AND DISPLAY DEVICE

• US 20160380005A1
• Filed: 04/14/2016
• Published: 12/29/2016
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: HOU, Xuecheng, LU, Kai, GUO, Jian
• Granted Patent: US 9,799,683 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film transistor and a resin layer having at least one resin via hole, wherein a film-thickness-difference-adjusting layer used for reducing the film thickness difference at the resin via hole is arranged at the lower part of the resin layer in at least a part of the resin via hole. By providing the film-thickness-difference-adjusting layer, the film thickness difference at the resin via hole can be effectively reduced, and when a photolithographic process is performed, the difference of the thickness of the photoresist here and the thicknesses at other positions is reduced, so that the via hole fluctuation of a passivation layer caused by the larger film thickness difference at the resin via hole is improved, and the metal residue problem of the pixel electrodes is effectively avoided.

Claims

1. An array substrate, comprising at least one thin film transistor and a resin layer having at least one resin via hole, the thin film transistor comprising a source electrode, a drain electrode, a gate electrode and an active layer, wherein an film-thickness-difference-adjusting layer used for reducing the film thickness difference at the resin via hole is arranged at the lower part of the resin layer in at least a part of the resin via hole.

2. The array substrate of claim 1, wherein the array substrate comprises a pixel region and a non-pixel region, the resin layer having the resin via hole is arranged in the pixel region, and the film-thickness-difference-adjusting layer is arranged at the lower part of the resin layer at the resin via hole in the pixel region.

3. The array substrate of claim 2, wherein the drain electrode is arranged in the resin layer in the pixel region, the resin via hole is formed in the resin layer above the drain electrode, the film-thickness-difference-adjusting layer is located below the drain electrode, and the projection of the film-thickness-difference-adjusting layer on the substrate and the projection of the drain electrode on the substrate at least partially overlap.

4. The array substrate of claim 3, wherein the pixel region further comprises a gate insulation layer, and the film-thickness-difference-adjusting layer is arranged between the gate insulation layer and the drain electrode.

5. The array substrate of claim 3, wherein the projections of the film-thickness-difference-adjusting layer and the drain electrode on the substrate completely overlap.

6. The array substrate of claim 1, wherein the resin layer is composed of photosensitive resin or non-photosensitive resin.

7. The array substrate of claim 1, wherein the thickness of the resin layer is 1.2-3.0 μ

m.

8. The array substrate of claim 1, wherein the film-thickness-difference-adjusting layer is the active layer.

9. The array substrate of claim 1, wherein the film-thickness-difference-adjusting layer is the gate electrode layer.

10. The array substrate of claim 1, wherein the thickness of the film-thickness-difference-adjusting layer is 0.2-0.35 μ

m.

14. A display device, comprising the array substrate of claim 1.

11. A preparation method of an array substrate comprising at least one thin film transistor and a resin layer having at least one resin via hole, the thin film transistor comprising a source electrode, a drain electrode, a gate electrode and an active layer, the preparation method of the array substrate comprising:

a step of forming a film-thickness-difference-adjusting layer, which is used for reducing the film thickness difference at the resin via hole, at the lower part of the resin layer in at least a part of the resin via hole.

12. The preparation method of the array substrate according to claim 11, wherein the step of forming the film-thickness-difference-adjusting layer is a step of forming the active layer.

13. The preparation method of the array substrate according to claim 11, wherein the step of forming the film-thickness-difference-adjusting layer is a step of forming the gate electrode.