HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE

• US 20160380078A1
• Filed: 04/06/2016
• Published: 12/29/2016
• Est. Priority Date: 06/25/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation
• Inventors: Bu, Huiming, Greene, Andrew M., Pranatharthiharan, Balasubramanian, Xie, Ruilong
• Granted Patent: US 9,721,834 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

Claims

1. A method for filling gaps between structures in a semiconductor device, comprising:

patterning a stack of layers including at least a gate material, a first dielectric layer and a hard mask layer to form a plurality of high aspect ratio structures adjacent to one another to provide gaps therebetween;

conformally depositing a spacer dielectric layer over the high aspect ratio structures;

removing the spacer dielectric layer from horizontal surfaces to form spacers on sidewalls of the high aspect ratio structures;

forming source and drain regions adjacent to the spacers;

conformally depositing a protection layer over the high aspect ratio structures and the source and drain regions;

filling the gaps with a flowable dielectric;

recessing the flowable dielectric to a height along the sidewalls of the high aspect ratio structures by a selective etch process such that the protection layer protects the spacers of the high aspect ratio structures;

exposing the first dielectric layer and the spacers by an etch process that selectively removes the hard mask and the protection layer above the height wherein the first dielectric layer and the spacer dielectric layer have a higher etch resistance than the hard mask and the protection layer to maintain a thickness of the spacers through the recessing step and the exposing step; and

filling the gaps by a high density plasma fill.

2. The method as recited in claim 1, wherein conformally depositing a spacer dielectric layer over the high aspect ratio structures includes conformally depositing the spacer dielectric layer with a material having a higher etch resistance than SiN.

3. The method as recited in claim 2, wherein the spacer dielectric layer includes SiBCN.

4. The method as recited in claim 1, wherein forming a first dielectric layer includes forming the first dielectric layer with a material having a higher etch resistance than SiN.

5. The method as recited in claim 4, wherein the first dielectric layer includes SiBCN.

6. The method as recited in claim 1, wherein conformally depositing a spacer dielectric layer over the high aspect ratio structures includes conformally depositing the spacer dielectric layer with a thickness of 12 nm or less to increase a gap size between high aspect ratio structures without altering a pitch between the high aspect ratio structures.

7. The method as recited in claim 6, wherein filling the gaps by a high density plasma fill includes avoiding formation of voids by providing the gap size that has been increased.

8. The method of claim 1, wherein the plurality of high aspect ratio structures includes a high to width ration greater than 1:

1.

9. The method of claim 1, wherein exposing the first dielectric layer and the spacers includes forming horns on top corners of the spacers.

10. The method of claim 1, further comprising:

removing the exposed first dielectric layer and the gate material between the spacers; and

forming a replacement metal gate between the spacers, wherein the replacement metal includes a high-k dielectric layer and a metal fill layer.

11. The method as recited in claim 1, further comprising forming contact holes by etching through the flowable dielectric and the protection layer.

12. The method of claim 11, further comprising forming contacts within the contact holes, wherein the contacts include a contact liner and a metal contact.

20. The device of claim 1, wherein the contacts include a contact liner and a metal contact.

13. A semiconductor device, comprising:

a plurality of high aspect ratio gate structures formed adjacent to one another and forming gaps therebetween, the high aspect ratio gate structures including a top surface;

spacers formed on sidewalls of the high aspect ratio structures, the spacers having a higher etch resistance than SiN in a selective oxide etch to maintain dimensions of the spacers during etch processes;

the gaps being filled with;

a protection layer formed on the spacers to a height on the spacers;

a flowable dielectric formed to below the height within the protection layer; and

a high density plasma dielectric fill above the height; and

contacts formed through the high density plasma dielectric fill, the flowable dielectric and the protection layer to connect to source and drain regions.

14. The device as recited in claim 13, wherein the spacers include SiBCN.

15. The device as recited in claim 13, wherein the spacers includes a thickness of 12 nm or less to increase a gap size between high aspect ratio gate structures without altering a pitch between the high aspect ratio gate structures.

16. The device as recited in claim 13, wherein the protection layer includes a nitride.

17. The device of claim 13, wherein the plurality of high aspect ratio structures includes a high to width ration greater than 1:

1.

18. The device of claim 13, wherein each of the plurality of high aspect ratio structures includes at least a gate material and a first dielectric layer.

19. The device of claim 18, wherein the spacers exceed a height of the gate material and the first dielectric layer such that the spacers form horns on top corners of the spacers.