VOLTAGE REDUCTION CIRCUIT

• US 20160380610A1
• Filed: 06/29/2016
• Published: 12/29/2016
• Est. Priority Date: 06/29/2015
• Status: Active Grant

• Current Assignee: ASM America Incorporated (ASM International NV)
• Original Assignee: Reno Technologies Inc.
• Inventors: Ulrich, Michael Gilliam
• Granted Patent: US 10,699,880 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32183 Matching circuits
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

In one embodiment, the invention can be an impedance matching network including an input configured to operably couple to a radio frequency (RF) source; an output configured to operably couple to a load; a first variable capacitor; a second variable capacitor; and a third capacitor in series with the second variable capacitor and reducing a voltage on the second variable capacitor.

Claims

1. An impedance matching network comprising:

an input configured to operably couple to a radio frequency (RF) source;

an output configured to operably couple to a load;

a first variable capacitor;

a second variable capacitor; and

a third capacitor in series with the second variable capacitor and reducing a voltage on the second variable capacitor.

2. The network of claim 1 wherein the load is a plasma chamber, and the reduced voltage is an alternating current or radio frequency voltage.

3. The network of claim 2 wherein the third capacitor is a non-variable capacitor.

4. The network of claim 3 wherein the first and second variable capacitors are electronically variable capacitors.

5. The network of claim 1 wherein:

the first variable capacitor forms part of a first shunt parallel to the RF source;

the second variable capacitor forms part of a second shunt parallel to the load; and

the second shunt comprises the third capacitor.

6. The network of claim 5 further comprising a fourth capacitor parallel to the second shunt.

7. The network of claim 1 wherein:

the first variable capacitor is in series with the input; and

the second variable capacitor is in series with the output.

8. The network of claim 1 wherein:

the first variable capacitor is parallel to the input; and

the second variable capacitor is in series with the output.

9. The network of claim 1 wherein the voltage on the second variable capacitor when the third capacitor is present is half or less than half of a voltage on the second variable capacitor when the third capacitor is not present.

10. The network of claim 1 wherein a capacitance value of the third capacitor is equal to a maximum capacitance value of the second capacitor.

11. The network of claim 1 wherein a capacitance value of the third capacitor is equal to a minimum capacitance value of the second capacitor.

12. An impedance matching network comprising:

an input;

an output;

a first variable capacitor;

a second variable capacitor; and

a third capacitor in series with the second variable capacitor;

wherein the first variable capacitor has a first capacitance, and the second variable capacitor has second capacitance; and

wherein the first capacitance and the second capacitance are configured to be altered to create an impedance match at the input.

13. The network of claim 12 wherein:

the first variable capacitor forms part of a first shunt parallel to the RF source;

the second variable capacitor forms part of a second shunt parallel to the output; and

the second shunt comprises the third capacitor.

14. The network of claim 13 further comprising a first inductor is located between the first shunt and the second shunt.

15. The network of claim 12 wherein a voltage drop on the second variable capacitor when the third capacitor is present is less than a voltage drop on the variable capacitors when the third capacitor is not present.

16. The network of claim 12 wherein a capacitance value of the third capacitor is equal to a maximum capacitance value of the second capacitor.

17. The network of claim 12 wherein a capacitance value of the third capacitor is equal to a minimum capacitance value of the second capacitor.

18. A method of matching an impedance comprising:

providing a matching network between an RF source and a load, the matching network comprising;

an input configured to operably couple to the RF source;

an output configured to operably couple to the load;

a first variable capacitor;

a second variable capacitor; and

a third capacitor in series with the second variable capacitor and reducing a voltage on the second variable capacitor; and

varying a capacitance of the first variable capacitor or the second variable capacitor to achieve an impedance match.

19. A method of manufacturing a semiconductor comprising:

operably coupling a matching network between an RF source and a plasma chamber, the plasma chamber configured to deposit a material layer onto the substrate or etch a material layer from the substrate, and the matching network comprising;

an input configured to operably couple to the RF source;

an output configured to operably couple to the plasma chamber;

a first variable capacitor;

a second variable capacitor; and

a third capacitor in series with the second variable capacitor and reducing a voltage on the second variable capacitor;

placing a substrate in the plasma chamber;

energizing plasma within the plasma chamber by coupling RF power from the RF source into the plasma chamber to perform a deposition or etching; and

controlling a capacitance of the first variable capacitor or the second variable capacitor to achieve an impedance match.

20. The method of claim 19 wherein:

the first variable capacitor forms part of a first shunt parallel to the RF source;

the second variable capacitor forms part of a second shunt parallel to the plasma chamber; and

the second shunt comprises the third capacitor.