COMPUTER ARCHITECTURE USING RAPIDLY RECONFIGURABLE CIRCUITS AND HIGH-BANDWIDTH MEMORY INTERFACES

• US 20160380635A1
• Filed: 06/26/2015
• Published: 12/29/2016
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Roberts, David A.
• Granted Patent: US 9,698,790 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 15/7892 Reconfigurable logic embedded in CPU, e.g. reconfigurable unit
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A programmable device comprises one or more programming regions, each comprising a plurality of configurable logic blocks, where each of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block via a programmable interconnect fabric. The programmable device further comprises configuration logic configured to, in response to an instruction in an instruction stream, reconfigure hardware in one or more of the configurable logic blocks in a programming region independently from any of the other programming regions.

Claims

1. A programmable device, comprising:

one or more programming regions, each comprising a plurality of configurable logic blocks, wherein each configurable logic block of the plurality of configurable logic blocks is selectively connectable to any other configurable logic block of the plurality of configurable logic blocks via a programmable interconnect fabric, wherein a first programming region of the one or more programming regions is configured to execute a first instruction in an instruction stream; and

configuration logic configured to, in response to a second instruction in the instruction stream, reconfigure hardware in one or more of the plurality of configurable logic blocks in the first programming region independently from any other programming region of the one or more programming regions, wherein the first programming region is configured to execute the second instruction using the reconfigured hardware in the one or more of the plurality of configurable logic blocks in the first programming region.

2. The programmable device of claim 1, wherein each programming region is coupled with a configuration memory configured to store a plurality of selectable configurations for the programming region, and the configuration logic is further configured to reconfigure the programming region based on a selected configuration of the plurality of selectable configurations stored in the configuration memory of the programming region.

3. The programmable device of claim 2, wherein the configuration memory comprises static random access memory (SRAM).

4. The programmable device of claim 2, wherein the configuration memory is located nearer to the programming region than to any other programming region.

5. The programmable device of claim 1, wherein the instruction stream is a continuous instruction stream including at least a subset of the instructions defining a single computer program, and wherein the second instruction is a next following instruction after the first instruction in the instruction stream.

6. The programmable device of claim 1, further comprising a set of boundary switches in the programmable interconnect fabric configured to electrically isolate one programming region from other programming regions.

7. The programmable device of claim 1, wherein the second instruction is a reconfiguration instruction that identifies the first programming region and identifies a selected configuration for the first programming region.

8. The programmable device of claim 1, further comprising a context memory configured to store context data for the first programming region prior to the reconfiguration of the hardware in the one or more configurable logic blocks.

9. The programmable device of claim 1, wherein the programmable device is a field-programmable gate array (FPGA) device.

10. The programmable device of claim 1, wherein the programmable device resides on one of a plurality of stacked dies coupled by through-silicon vias (TSVs).

11. The programmable device of claim 1, further comprising a function table configured to store an address of a configuration bitstream for each of a plurality of instructions, wherein the configuration logic is further configured to identify from the function table an address of a configuration bitstream corresponding to the second instruction.

12. A method, comprising:

in response to receiving a first instruction in an instruction stream, executing the first instruction in a first programming region of one or more programming regions in a programmable device;

in response to receiving a second instruction in the instruction stream, reconfiguring hardware in one or more of a plurality of configurable logic blocks in the first programming region independently from any other programming region of the one or more programming regions; and

executing the second instruction using the reconfigured hardware in the one or more of the plurality of configurable logic blocks in the first programming region.

13. The method of claim 12, further comprising, for each programming region of the one or more programming regions:

storing a plurality of selectable configurations for the programming region; and

reconfiguring the programming region based on a selected configuration of the plurality of selectable configurations stored in the configuration memory of the programming region.

14. The method of claim 13, wherein the second instruction is a reconfiguration instruction that identifies the first programming region and identifies the selected configuration for the first programming region, and wherein reconfiguring the first programming region comprises selecting one of the plurality of selectable configurations stored in the configuration memory of the first programming region based on the second instruction.

15. The method of claim 12, wherein the instruction stream is a continuous instruction stream including at least a subset of instructions defining a single computer program, and wherein the second instruction is a next following instruction after the first instruction in the instruction stream.

16. The method of claim 12, further comprising, isolating the first programming region from other programming regions of the one or more programming regions via a set of boundary switches in a programmable interconnect fabric that connects the plurality of configurable logic blocks.

17. The method of claim 12, further comprising storing context data for the first programming region in a context memory prior to reconfiguring the hardware in the one or more configurable logic blocks.

18. The method of claim 12, wherein the programmable device is a field-programmable gate array (FPGA) device.

19. The method of claim 12, wherein the programmable device resides on one of a plurality of stacked dies coupled by through-silicon vias (TSVs).

20. The method of claim 12, further comprising:

storing in a function table an address of a configuration bitstream for each of a plurality of instructions; and

identifying from the function table an address of a configuration bitstream corresponding to the second instruction.

21. A computing system, comprising:

a processor configured to dispatch a plurality of instructions in an instruction stream; and

a programmable device coupled with the processor, the programmable device comprising;

one or more programming regions, each comprising a plurality of configurable logic blocks, wherein each configurable logic block is selectively connectable to any other configurable logic block via a programmable interconnect fabric, wherein a first programming region of the one or more programming regions is configured to execute a first instruction in an instruction stream; and

configuration logic configured to, in response to a second instruction in the instruction stream, reconfigure hardware in one or more of the plurality of configurable logic blocks in the first programming region independently from any other programming region, wherein the first programming region is configured to execute the second instruction using the reconfigured hardware in the one or more of the plurality of configurable logic blocks in the first programming region.

22. The computing system of claim 21, further comprising, for each programming region, a configuration memory configured to store a plurality of selectable configurations for the programming region, wherein the configuration memory is located in a dynamic random access memory (DRAM) module stacked above the programmable device, and wherein the configuration memory is coupled to the programming region by one or more through-silicon vias.

23. The computing system of claim 22, further comprising a memory controller coupled with the configuration memory and configured to receive a selected configuration of the plurality of selectable configurations from the configuration memory and apply the selected configuration to the programmable device.

24. The computing system of claim 21, wherein the programmable device comprises a field programmable gate array (FPGA) device.

25. The computing system of claim 21, wherein a first integrated circuit die including the programmable device is stacked above a second integrated circuit die including the processor, and wherein the first integrated circuit die and the second integrated circuit die are coupled by through-silicon vias (TSVs).

26. The computing system of claim 21, further comprising a function table configured to store an address of a configuration bitstream for each of a plurality of instructions, wherein the configuration logic is further configured to identify from the function table an address of a configuration bitstream corresponding to the second instruction.

27. The computing system of claim 21, wherein the configuration logic is configured to reconfigure the hardware in the one or more of the plurality of configurable blocks by reconfiguring the hardware from a first hardware configuration to a second hardware configuration;

and wherein the computing system further comprises a compiler configured to;

based on input source code, identify a third instruction executable in the first programming region when the hardware is in the second hardware configuration; and

in response to identifying the third instruction, generating the second instruction prior to the third instruction in the instruction stream.