CDR CONTROL CIRCUIT, CDR CIRCUIT, AND CDR CONTROL METHOD

• US 20160380638A1
• Filed: 04/29/2016
• Published: 12/29/2016
• Est. Priority Date: 06/26/2015
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: KUMAZAWA, Makoto
• Granted Patent: US 9,705,510 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A CDR control circuit detects a phase shift of input data that is taken in with a phase-adjusted clock, and generates phase control data that controls the phase of the clock based on the detected phase shift, the CDR control circuit includes a change detection circuit that detects an over-change in the phase shift; and a selection circuit that outputs the phase shift before the change, which is the phase shift before the time of detection of the over-change, as the phase shift for a predetermined period of time at the time of detection of the over-change, wherein during the predetermined period of time, the phase control data is generated based on the phase shift before change.

Claims

1. A CDR control circuit that detects a phase shift of input data that is taken in with a phase-adjusted clock, and generates phase control data that controls the phase of the clock based on the detected phase shift, the CDR control circuit comprising:

a change detection circuit that detects an over-change in the phase shift; and

a selection circuit that outputs the phase shift before the change, which is the phase shift before the time of detection of the over-change, as the phase shift for a predetermined period of time at the time of detection of the over-change, wherein

during the predetermined period of time, the phase control data is generated based on the phase shift before change.

2. The CDR control circuit according to claim 1, further comprising a storage circuit that stores the phase shift, wherein

the change detection circuit:

calculates a difference between the phase shift at a time a first time before the time of detection of the over-change, the phase shift being stored in the storage circuit, and the current phase shift as an amount of change; and

compares a limit of the phase shift at the time the first time before, the limit being determined from a maximum amount of change that can be followed up, and the calculated amount of change, and determines that the over-change has occurred when the amount of change exceeds the limit.

3. The CDR control circuit according to claim 2, wherein

the selection circuit:

outputs data of the phase shift during a period of time other than the predetermined period of time after the time of detection of the over-change; and

outputs data of the phase shift at a time a second time before, the second time being longer than the first time, as data of the phase shift before change during the predetermined period of time after the time of detection of the over-change.

4. The CDR control circuit according to claim 2, wherein

the change detection circuit latches and holds the phase shift at the time the first time before when detecting that the calculated amount of change is smaller than a first threshold value, and outputs the held phase shift as the phase shift before change.

5. The CDR control circuit according to claim 2, wherein

the storage circuit includes:

a divider circuit that generates a divided clock of a base clock in synchronization with the change in the phase shift; and

latch circuits in a plurality of stages formed so that the phase shift is input in the initial stage and an output of the initial stage is input in the second stage, an output of the second stage is input in the third stage, and so on, and latching in each stage is performed in synchronization with the divided clock or a reversed clock of the divided clock,

the change detection circuit calculates a difference between the output in the latch circuit in the plurality of stages other than the initial stage and the current phase shift as an amount of change, and

the selection circuit outputs the output in the stage after the stage that is used by the change detection circuit to calculate the amount of change of the latch circuits in the plurality of stages as the phase shift during the predetermined period of time at the time of detection of the over-change.

6. The CDR control circuit according to claim 2, wherein

the selection circuit changes the length of the predetermined period of time during which the selection circuit outputs the phase shift before change in accordance with the value of the amount of change when the amount of change detected by the change detection circuit exceeds the limit.

7. The CDR control circuit according to claim 1, further comprising a storage circuit that stores the phase shift, wherein

the change detection circuit:

includes a counter that adds or subtracts phase data indicating the delayed phase or advanced phase of the detected input data during the predetermined period of time; and

determines that the over-change has occurred when the absolute value of the count value of the counter exceeds a threshold value.

8. A CDR circuit comprising:

a phase adjustment circuit that adjusts a phase of a multiphase reference clock to a phase corresponding to phase control data and generates a multiphase-adjusted clock;

a latch circuit that takes in input data with a multiphase-adjusted clock;

a de-serializer that converts a latched signal into parallel data; and

a CDR control circuit that detects a phase shift from the parallel data and generates the phase control data based on the detected phase shift, wherein,

the CDR control circuit includes;

a change detection circuit that detects an over-change in the phase shift; and

a selection circuit that outputs a phase shift before change, which is the phase shift before the time of detection of the over-change, as the phase shift during a predetermined period of time at the time of detection of the over-change, during the predetermined period of time, the phase control data being generated based on the phase shift before change.

9. A CDR control method of detecting a phase shift of input data that is taken in with a phase-adjusted clock and generating phase control data that controls the phase of the clock based on the detected phase shift, the method comprising:

after an initial lock is completed,

detecting the current phase shift;

updating and holding a phase shift at a time a second time before the current time;

calculating a difference between the phase shift at a time the first time before the current time and the current phase shift as an amount of change, and comparing the amount of change with a limit value of the phase shift per the first time;

performing a CDR normal operation to generate the phase control data based on the current phase shift in a case where the amount of change does not exceed the limit value, suspending the CDR normal operation in a case where the amount of change exceeds the limit value, and generating the phase control data based on the phase shift at the time the second time before during a predetermined period of time; and

resuming, after the predetermined period of time elapses, the CDR normal operation to generate the phase control data based on the current phase shift.

10. The CDR control method according to claim 9, wherein

the limit value is set from a maximum changeable value and a necessary amount of change by calculating the maximum changeable value of the phase shift per the first time from a setting of an object to be controlled and by calculating the necessary amount of change in the phase shift per the first time from control quality of the object to be controlled.