VARIABLE CODE RATE SOLID-STATE DRIVE

• US 20170004031A1
• Filed: 07/01/2015
• Published: 01/05/2017
• Est. Priority Date: 07/01/2015
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Dick, Christopher H.
• Granted Patent: US 9,727,416 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/353 Adaptation to the channel
• CPC Class Codes: H03M 13/635 Error control coding in combination with rate matching
• CPC Class Codes: H03M 13/6393 Rate compatible low-density parity check [LDPC] codes

Abstract

An apparatus, as well as a method therefor, relates generally to managing reliability of a solid state storage. In such an apparatus, there is a memory controller for providing a code rate. An encoder is for receiving input data and the code rate for providing encoded data. The solid-state storage is for receiving and storing the encoded data. A decoder is for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed. The decoded data is provided as soft decisions representing probabilities of the decoded data. The memory controller is for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data.

Claims

1. A method for managing reliability of a solid-state storage, comprising:

reading encoded data stored in the solid-state storage;

decoding the encoded data accessed to provide decoded data as soft decisions representing probabilities of the decoded data;

assessing the probabilities of the decoded data; and

adjusting a code rate of an encoder and a decoder responsive to the assessment.

2. The method according to claim 1, wherein the code rate is for a linear error correcting code.

3. The method according to claim 2, wherein the solid-state storage comprises memory cells selected from a group consisting of multi-level cells, binary cells, triple-level cells, and single-level cells for storage of the encoded data.

4. The method according to claim 2, wherein:

the encoder is a Low-Density Parity-Check encoder; and

the decoder is an LDPC decoder.

5. The method according to claim 1, further comprising:

encoding input data with the encoder to provide the encoded data; and

writing the encoded data to the solid-state storage.

6. The method according to claim 5, wherein the accessing comprises reading a predefined amount of the encoded data from the solid-state storage.

7. The method according to claim 6, wherein the predefined amount is selected from a group consisting of a sector, a block, a subarray, and an array of the solid-state storage.

8. The method according to claim 1, wherein the code rate is a first code rate, the method further comprising:

determining soft bits for the decoded data;

combining magnitudes of the soft bits for the decoded data to provide a metric therefor; and

determining a second code rate lower than the first code rate to use responsive to the metric.

9. The method according to claim 8, further comprising blocking use of a predefined amount of the solid-state storage responsive to the metric.

10. The method according to claim 9, wherein:

the blocking includes address mapping to prevent use of the predefined amount; and

the predefined amount includes at least one block of a sector of the solid-state storage.

11. An apparatus for managing reliability of a solid state storage, comprising:

a memory controller for providing a code rate;

an encoder for receiving input data and the code rate for providing encoded data;

the solid-state storage for receiving and storing the encoded data;

a decoder for accessing the encoded data stored in the solid-state storage and for receiving the code rate for providing decoded data of the encoded data accessed;

the decoded data being provided as soft decisions representing probabilities of the decoded data; and

the memory controller for receiving the decoded data for adjusting the code rate responsive to the probabilities of the decoded data.

12. The apparatus according to claim 11, wherein the code rate is for a linear error correcting code.

13. The apparatus according to claim 11, wherein the solid-state storage comprises memory cells selected from a group consisting of multi-level cells, binary cells, triple-level cells, and single-level cells for storage of the encoded data.

14. The apparatus according to claim 11, wherein:

the encoder is a Low-Density Parity-Check (“

LDPC”

) encoder; and

the decoder is an LDPC decoder.

15. The apparatus according to claim 11, wherein the decoder is a soft-in soft-out decoder.

16. The apparatus according to claim 11, wherein the solid-state storage is configured to read out the encoded data in a predefined amount.

17. The apparatus according to claim 16, wherein the predefined amount is selected from a group consisting of a sector, a block, a subarray, and an array of the solid-state storage.

18. The apparatus according to claim 11, wherein:

the decoder is configured to provide soft bits representing the probabilities for the decoded data; and

the memory controller is configured to combine magnitudes of the soft bits for the decoded data to provide a metric for selecting the code rate.

19. The apparatus according to claim 18, wherein the memory controller is further configured to:

compare the metric to a threshold; and

determine an adjustment of the code rate responsive to the metric being below the threshold.

20. The apparatus according to claim 18, wherein the memory controller is further configured to:

point to the code rate in a store of code rates with the metric as a pointer; and

output, from the store of the code rates, the code rate pointed to.