FINFET with U-Shaped Channel

• US 20170005090A1
• Filed: 06/30/2015
• Published: 01/05/2017
• Est. Priority Date: 06/30/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ando, Takashi, Dennard, Robert H., Lauer, Isaac, Muralidhar, Ramachandran, Shahidi, Ghavam G.
• Granted Patent: US 9,627,378 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0257 Doping during depositing
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin

Abstract

In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

Claims

1. A method of forming fin field-effect transistor (FET) devices, the method comprising the steps of:

patterning fins in a wafer;

forming a doped epitaxial cladding layer on the fins prior to forming dummy gates, wherein the doped epitaxial cladding layer is in-situ doped with an n-type or a p-type dopant;

forming the dummy gates over portions of the fins that serve as channel regions of the finFET device;

forming spacers on opposite sides of the dummy gates;

depositing a gap fill oxide on the wafer, filling any gaps between the spacers;

removing the dummy gates forming gate trenches;

trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and

forming replacement gate stacks in the gate trenches over the portions of the fins that serve as the channel regions of the finFET devices, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

3. The method of claim 1, wherein the doped epitaxial cladding layer comprises epitaxial silicon, germanium, or silicon germanium.

5. The method of claim 1, wherein the step of trimming the fins within the gate trenches removes at least a portion of the doped epitaxial cladding layer from the fins within the gate trenches.

6. The method of claim 1, wherein the width of the fins outside of the gate trenches is from about 7 nanometers to about 20 nanometers, and ranges therebetween.

7. The method of claim 1, wherein the width of the fins within the gate trenches is from about 3 nanometers to about 10 nanometers, and ranges therebetween.

8. The method of claim 1, wherein the dummy gates comprise poly-silicon.

9. The method of claim 1, wherein the step of forming the replacement gate stacks comprises the steps of:

depositing a conformal gate dielectric material into and lining the gate trenches and covering the fins;

depositing a conformal workfunction setting metal layer into the gate trenches on the conformal gate dielectric; and

depositing a filler gate metal into and filling the gate trenches.

10. The method of claim 9, wherein the conformal gate dielectric includes a high-κ

material selected from the group consisting of hafnium oxide and lanthanum oxide.

11. The method of claim 9, wherein the conformal workfunction setting metal layer comprises an n-type workfunction metal selected from the group consisting of:

titanium nitride, tantalum nitride, and aluminum-containing alloys.

12. The method of claim 9, wherein the conformal workfunction setting metal layer comprises a p-type workfunction metal selected from the group consisting of:

titanium nitride, tantalum nitride, and tungsten.

13. The method of claim 9, wherein the filler gate metal comprises tungsten or aluminum.

14. The method of claim 1, further comprising the step of:

using a fin hardmask to pattern the fins in the wafer.

15. The method of claim 14, further comprising the step of:

removing the fin hardmask from the fins prior to forming the dummy gates.

16. The method of claim 14, further comprising the steps of:

trimming the fin hardmask prior to trimming the fins; and

removing the fin hardmask after trimming the fins.

2. (canceled)

4. (canceled)

17-21. -21. (canceled)

22. A method of forming fin FET devices, the method comprising the steps of:

patterning fins in a wafer using a fin hardmask;

forming a doped epitaxial cladding layer on the fins prior to forming dummy gates, wherein the doped epitaxial cladding layer is in-situ doped with an n-type or a p-type dopant;

forming the dummy gates over portions of the fins that serve as channel regions of the finFET device;

forming spacers on opposite sides of the dummy gates;

depositing a gap fill oxide on the wafer, filling any gaps between the spacers;

removing the dummy gates forming gate trenches;

trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches, the method further comprising trimming the fin hardmask prior to trimming the fins and removing the fin hardmask after trimming the fins; and

forming replacement gate stacks in the gate trenches over the portions of the fins that serve as the channel regions of the finFET devices, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.