HYBRID PIXEL SENSOR ARRAY

• US 20170006236A1
• Filed: 11/28/2014
• Published: 01/05/2017
• Est. Priority Date: 11/29/2013
• Status: Active Grant

• Current Assignee: UK Research and Innovation
• Original Assignee: Science and Technology Facilities Council
• Inventors: FRENCH, Marcus Julian, VEALE, Matthew Charles
• Granted Patent: US 9,843,741 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1465 of the hybrid type
• CPC Class Codes: H01L 27/14661 of the hybrid type
• CPC Class Codes: H01L 27/14806 Structural or functional details thereof
• CPC Class Codes: H04N 25/30 for transforming X-rays into image signals
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/713 Transfer or readout registers; Split readout registers or multiple readout registers
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor
• CPC Class Codes: H04N 5/32 Transforming X-rays cameras or camera modules for generating image signals from X-rays H04N23/30; circuitry of SSIS for transforming X-rays into image signals H04N25/30

Abstract

A hybrid pixel sensor array is provided. Each pixel of the array comprises: a sensor for generating an imaging signal; a Charged-Coupled Device (CCD) array, coupled to the sensor so as to receive samples from the imaging signal and configured for storage of a plurality of samples; and active CMOS circuitry, coupled to the CCD array for generating a pixel output signal from the stored samples. The sensors of the pixels are part of a sensor portion of the hybrid pixel sensor array that is separate from both the CCD array and active CMOS circuitry of the pixels.

Claims

1. A hybrid pixel sensor array, each pixel of the array comprising:

a sensor for generating an imaging signal;

a Charged-Coupled Device, CCD, array, coupled to the sensor so as to receive samples from the imaging signal and configured for storage of a plurality of samples; and

active CMOS circuitry, coupled to the CCD array for generating a pixel output signal from the stored samples; and

wherein the sensors of the pixels are part of a sensor portion of the hybrid pixel sensor array that is separate from both the CCD array and active CMOS circuitry of the pixels.

2. The hybrid pixel sensor array of claim 1, wherein the sensor portion is a sensor tile on which the sensors of the pixel are arranged in a two-dimensional array, the sensor tile being separated from the CCD array and active CMOS circuitry of the pixels in a third dimension, different from the two dimensions of the array.

3. The hybrid pixel sensor array of claim 2, wherein the CCD array and active CMOS circuitry of the pixels are formed on a readout Application Specific Integrated Circuit, ASIC and wherein the sensor tile is bonded to the readout ASIC.

4. The hybrid pixel sensor array of claim 3, wherein the sensor tile is bonded to the readout ASIC using at least one bump-bond pad.

5. The hybrid pixel sensor array of claim 4, wherein the at least one bump-bond pad comprises Indium.

6. The hybrid pixel sensor array of claim 3, wherein the sensor tile is bonded to the readout ASIC using solder.

7. The hybrid pixel sensor array of claim 3, wherein the sensor tile is bonded to the readout ASIC in a flip-chip arrangement.

8. The pixel sensor array of claim 3, wherein the bonding between the sensor tile and the readout ASIC provides coupling between the sensor of each pixel on the sensor tile and the CCD array of the respective pixel on the readout ASIC.

9. The hybrid pixel sensor array of claim 1, wherein the pitch of the sensor for each pixel is no greater than 60 microns.

10. The hybrid pixel sensor array of claim 1, further comprising biasing circuitry, configured to provide a biasing voltage across the sensor of each pixel.

11. The hybrid pixel sensor array of claim 1, wherein the sensor of each pixel is formed from GaAs.

12. The hybrid pixel sensor array of claim 11, wherein the sensor of each pixel is formed from GaAs compensated with chromium.

13. The hybrid pixel sensor array of claim 1, wherein the sensor of each pixel is an X-ray sensor.

14. The hybrid pixel sensor array of claim 1, wherein each pixel of the array further comprises:

interface CMOS circuitry, coupled to the sensor and configured to receive the imaging signal and provide the samples from the imaging signal to the CCD array.

15. The hybrid pixel sensor array of claim 14, wherein the imaging signal is a current signal, the interface CMOS circuitry comprising a charge amplifier, configured to sense the imaging signal and provide the samples from the imaging signal as voltage signals to the CCD array.

16. The hybrid pixel sensor array of claim 14, wherein the interface CMOS circuitry comprises an integrator or charge integration node.

17. The hybrid pixel sensor array of claims 14, wherein the interface CMOS circuitry comprises a reset device for the sensor of the pixel.

18. The hybrid pixel sensor array of claim 1, further comprising a transfer gate between the sensor and the CCD array.

19. The hybrid pixel sensor array of claim 1, wherein the CCD array comprises a pass entry gate, configured to receive the samples from the detection signal.

20. The hybrid pixel sensor array of claim 1, wherein the CCD array comprises a pass exit gate, arranged to couple to the active CMOS circuitry.

21. The hybrid pixel sensor array of claim 1, wherein the active CMOS circuitry comprises:

a source follower transistor, having a gate that is arranged to receive the stored samples of the imaging signal from the CCD array;

a row select transistor arranged in series with the source follower transistor, and having a gate that is configured to receive a row select signal; and

a reset transistor having a gate that is configured to receive a reset signal and a source and drain that are coupled between a reference DC voltage and the gate of the source follower transistor.

22. The hybrid pixel sensor array of claim 1, wherein the CCD array comprises at least one row of CCD registers, each row of CCD registers comprising:

a first vertical CCD register;

a series configuration of one or more lateral CCD registers coupled to the first vertical CCD register at one end; and

a second vertical CCD register coupled to the other end of the series configuration of one or more lateral CCD registers.

23. The hybrid pixel sensor array of claim 22, wherein each row of CCD registers further comprises:

a buffer entry gate arranged to couple the first vertical CCD register to the series configuration of one or more lateral CCD registers; and

a buffer exit gate arranged to couple the series configuration of one or more lateral CCD registers to the second vertical CCD register.

24. The hybrid pixel sensor array of claim 22, wherein each CCD register comprises a plurality of gates in a series configuration.

25. The hybrid pixel sensor array of claim 24, wherein each CCD register comprises first, second and third gates in a series configuration, wherein the second gate of each first vertical CCD register of each row is coupled to the buffer entry gate and wherein the second gate of each second vertical CCD register of each row is coupled to the buffer exit gate.

26. The hybrid pixel sensor array of claims 22, wherein the CCD array comprises a plurality of rows of CCD registers, wherein the first vertical CCD registers of the rows are connected in series and wherein the second vertical CCD registers of the rows are connected in series.

27. The hybrid pixel sensor array of claim 26, wherein each CCD register comprises first, second and third gates in a series configuration, wherein the first vertical CCD registers of the rows are connected in series such that the third gate of the first vertical CCD register of one row is coupled to the first gate of the first vertical CCD register of the row directly beneath the one row and wherein the second vertical CCD registers of the rows are connected in series such that the third gate of the second vertical CCD register of one row is coupled to the second gate of the first vertical CCD register of the row directly beneath the one row.

28. The hybrid pixel sensor array of claim 26, wherein each CCD register comprises first, second and third gates in a series configuration and wherein the one or more lateral CCD registers of each row are connected in series such that the third gate of one lateral CCD register of a row is coupled to the first gate of a lateral CCD register of the row that is immediately adjacent the one lateral CCD register and closer to the second vertical CCD register of the row than the one lateral CCD register.

29. The hybrid pixel sensor array of claim 27, wherein:

the first gate of the first vertical CCD register of the first row is arranged to receive the samples from the detection signal; and

the third gate of the second vertical CCD register of the last row is arranged to couple to the active CMOS circuitry.

30. An hybrid imaging sensor comprising the hybrid pixel sensor array of claim 1.

31. The hybrid imaging sensor of claim 30, further comprising:

addressing circuitry for activating one or more pixels of the hybrid pixel sensor array; and

readout circuitry, for receiving the pixel output signal for each pixel activated by the addressing circuitry.

32. The hybrid imaging sensor of claim 31, wherein the hybrid pixel sensor array is arranged in two dimensions as rows and columns of pixels, the addressing circuitry being configured to activate a row of pixels at any one time and wherein the readout circuitry, is arranged to receive the pixel output signal for each pixel in the activated row at the same time.