ADAPTIVE TEST TIME REDUCTION

• US 20170010325A1
• Filed: 07/08/2015
• Published: 01/12/2017
• Est. Priority Date: 07/08/2015
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Subbarayan, Arul, Badole, Sachin, Matta, Archana, Hegde, Madhura, Mier, Sergio, Plowman, Glenn Mark, Krishnan, Prakash, Bhat, Shankarnarayan, Laisne, Michael
• Application Number:
  US14/794,635
• Publication Number:
  US 20170010325A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318371 Methodologies therefor, e.g. algorithms, procedures

Abstract

A method and apparatus for adaptive test time reduction is provided. The method begins with running a predetermined number of structural tests on wafers or electronic chips. Pass/fail data is collected once the predetermined number of structural tests have been run. This pass/fail data is then used to determine which of the predetermined number of structural tests are consistently passed. The consistently passed tests are then grouped into slices within the test vectors. Once the grouping has been performed, the consistently passed tests are skipped when testing future production lots of the wafers or electronic chips. A sampling rate may be modulated if it is determined that adjustments in the tests performed are needed. In addition, a complement of the tests performed on the wafers may be performed on the electronic chips to ensure complete test coverage.

Claims

1. A method for adaptive test time reduction, comprising:

running a predetermined number of structural tests on multiple production lots of electronic components;

collecting pass/fail data for the predetermined number of structural tests;

determining which of the predetermined structural tests are consistently passed;

grouping the consistently passed structural tests into slices within test vectors;

skipping the consistently passed structural tests when testing future production lots of the electronic components; and

performing only those structural tests that produce failures.

2. The method of claim 1, further comprising:

analyzing the structural test generating failures to identify defects causing rejection of electronic components.

3. The method of claim 1, wherein the electronic device is a wafer.

4. The method of claim 1, wherein the electronic device is an electronic chip at a final testing stage.

5. The method of claim 1, wherein a first test vector is a test setup slice.

6. The method of claim 5, wherein second and subsequent test vectors contain slices of structural tests that produce failures.

7. The method of claim 6, wherein the slices containing structural tests that produce failures are added to a test flow as a burst that calls individual slices.

8. The method of claim 2, wherein the analyzing the structural tests generating failures also determines a minimum number of slices producing the failures.

9. The method of claim 1, further comprising:

performing only those structural tests that produce failures on a production lot of wafers;

determining which wafers pass the structural tests that produce failures; and

performing the structural test that produce failures again as a final test after completing fabrication of electronic chips fabricated from the passing wafers.

10. The method of claim 1, further comprising:

modulating a sampling rate in response to collecting pass/fail data for the predetermined number of structural tests.

11. The method of claim 9, wherein the final test is a complement of the structural tests producing failures in wafers.

12. An apparatus for test time reduction, comprising:

means for running a predetermined number of structural tests on multiple production lots of electronic components;

means for collecting pass/fail data for the predetermined number of structural tests;

means for determining which of the predetermined structural tests are consistently passed;

means for grouping the consistently passed structural tests into slices within test vectors;

means for skipping the consistently passed structural tests when testing future production lots of the electronic components; and

means for performing only those structural tests that produce failures.

13. The apparatus of claim 12, further comprising:

means for analyzing the structural tests generating failures to identify defects causing rejection of the electronic components.

14. The apparatus of claim 13, wherein the means for analyzing the structural tests generating failures also determines a minimum number of slices producing the failures.

15. The apparatus of claim 12, further comprising:

means for performing only those structural tests that produce failures on a production lot of wafers;

means for determining which wafers pass the structural tests that produce failures; and

means for performing the structural test that produce failures again as a final test after completing fabrication of electronic chips fabricated from the passing wafers.

16. The apparatus of claim 12, further comprising:

means for modulating a sampling rate in response to collecting pass/fail data for the predetermined number of structural tests.

17. A non-transitory computer-readable medium containing instructions, which when executed cause a processor to perform the steps of:

running a predetermined number of structural tests on multiple production lots of electronic components;

collecting pass/fail data for the predetermined number of structural tests;

determining which of the predetermined structural tests are consistently passed;

grouping the consistently passed structural tests into slices within test vectors;

skipping the consistently passed structural tests when testing future production lots of the electronic components; and

performing only those structural tests that produce failures.

18. The non-transitory computer-readable medium of claim 17, further comprising instructions for:

analyzing the structural test generating failures to identify defects causing rejection of electronic components.

19. The non-transitory computer-readable medium of claim 18, wherein the analyzing the structural tests generating failures also determines a minimum number of slices producing the failures.

20. The non-transitory computer-readable medium of claim 17, further comprising instructions for:

modulating a sampling rate in response to collecting pass/fail data for the predetermined number of structural tests.