EMBEDDED REFRESH CONTROLLERS AND MEMORY DEVICES INCLUDING THE SAME
First Claim
1. An embedded refresh controller included in a memory device, the embedded refresh controller comprising:
- a refresh counter configured to generate a counter refresh address signal in response to a counter refresh signal, the counter refresh address signal corresponding to a row address of the memory device; and
an address generator configured to store information with respect to a hammer address that is accessed intensively and configured to generate a hammer refresh address signal in response to a hammer refresh signal, the hammer refresh address signal corresponding to an address of a first row of the memory device that is physically adjacent to a second row of the memory device corresponding to the hammer address.
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Accused Products
Abstract
Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.
70 Citations
20 Claims
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1. An embedded refresh controller included in a memory device, the embedded refresh controller comprising:
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a refresh counter configured to generate a counter refresh address signal in response to a counter refresh signal, the counter refresh address signal corresponding to a row address of the memory device; and an address generator configured to store information with respect to a hammer address that is accessed intensively and configured to generate a hammer refresh address signal in response to a hammer refresh signal, the hammer refresh address signal corresponding to an address of a first row of the memory device that is physically adjacent to a second row of the memory device corresponding to the hammer address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory device comprising:
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a memory cell array including a plurality of memory cells; and an embedded refresh controller configured to control a refresh operation of the memory cells, the embedded refresh controller comprising; a refresh counter configured to generate a counter refresh address signal in response to a counter refresh signal, the counter refresh address signal corresponding to a row address of the memory cell array; and an address generator configured to store information with respect to a hammer address that is accessed intensively and configured to generate a hammer refresh address signal in response to a hammer refresh signal, the hammer refresh address signal corresponding to an address of a first row of the memory cell array that is physically adjacent to a second row of the memory cell array corresponding to the hammer address. - View Dependent Claims (13, 14, 15)
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16. A memory device comprising:
an embedded refresh controller comprising an address generator that is configured to store addresses of rows and numbers of occurrence of access to the respective rows and is configured to determine a hammer address as the address of one of the rows that has a highest number of occurrence of access in response to a hammer refresh signal. - View Dependent Claims (17, 18, 19, 20)
Specification