SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20170012000A1
• Filed: 09/03/2015
• Published: 01/12/2017
• Est. Priority Date: 07/06/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tseng, I-Ming, Liang, Wen-An, Huang, Chen-Ming
• Granted Patent: US 9,653,402 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.

Claims

1. A semiconductor device, comprising:

a fin structure disposed on a substrate, wherein the fin structure has a trench;

a first liner disposed in the trench;

a first insulating layer disposed on the first liner;

a shallow trench isolation disposed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer; and

a dummy gate structure disposed on the first insulating layer and disposed right above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.

3. The semiconductor device according to claim 1, wherein the shallow trench isolation has a depth greater than a depth of the trench.

4. The semiconductor device according to claim 1, wherein the dummy gate structure further comprises:

a dummy gate electrode disposed on the trench, wherein a portion of the dummy gate electrode is in the trench; and

a spacer disposed on the fin structure, surrounding the dummy gate electrode.

5. The semiconductor device according to claim 4, further comprising:

a second liner disposed between the spacer of the dummy gate structure and the top surface of the fin structure.

6. The semiconductor device according to claim 1, wherein a top surface of the first liner, a top surface of the first insulating layer and the top surface of the fin structure are on a same level.

7. The semiconductor device according to claim 1, further comprising a contact etching stop layer disposed on the fin structure and on the dummy gate structure.

8. The semiconductor device according to claim 1, further comprising at least one gate structure disposed on the fin structure.

9. The semiconductor device according to claim 8, further comprising at least one contact plug electrically contacted to the gate structure.

2. (canceled)

10. A method for forming a semiconductor device, comprising:

providing a substrate having a fin structure disposed thereon, wherein the fin structure has a trench;

forming a first liner in the trench;

forming a first insulating layer on the first liner; and

forming a dummy gate structure on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.

11. The method of claim 10, further comprising forming a shallow trench isolation in the substrate, and surrounding the fin structure.

12. The method of claim 11, wherein the shallow trench isolation has a depth greater than a depth of the trench.

13. The method of claim 10, wherein the dummy gate structure further comprises:

a dummy gate electrode disposed on the trench, wherein a portion of the dummy gate electrode is in the trench; and

a spacer disposed on the fin structure, surrounding the dummy gate electrode.

14. The method of claim 13, further comprising:

forming a second liner between the spacer of the dummy gate structure and the top surface of the fin structure.

15. The method of claim 10, wherein a top surface of the first liner, a top surface of the first insulating layer and the top surface of the fin structure are on a same level.

16. The method of claim 10, further comprising forming a contact etching stop layer on the fin structure and on the dummy gate structure.

17. The method of claim 10, further comprising forming at least one gate structure on the fin structure.

18. The method of claim 17, further comprising forming at least one contact plug electrically contacted to the gate structure.