Array Substrate and Manufacturing Method Thereof, Display Device

• US 20170012060A1
• Filed: 05/19/2016
• Published: 01/12/2017
• Est. Priority Date: 07/10/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: ZHANG, Hepan, AI, Qingnan, LI, Yue
• Granted Patent: US 10,388,672 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Abstract

A manufacturing method of an array substrate is disclosed. The manufacturing method includes a step of forming a pattern including a pixel electrode; and the manufacturing method further includes a step of forming a pattern including an active layer after the step of forming the pattern including the pixel electrode. Accordingly, an array substrate and a display device are also disclosed. In the manufacturing process of the array substrate, conductive material remained on the active layer is less, thereby producing less leak current, which in turn improves quality of the array substrate and display performance of the display device.

Claims

1. A manufacturing method of an array substrate, which includes a step of forming a pattern including a pixel electrode;

and

the manufacturing method further includes a step of forming a pattern including an active layer after the step of forming the pattern including the pixel electrode.

2. The manufacturing method according to claim 1, wherein the manufacturing method further includes a step of forming a pattern including a gate and forming a gate insulation layer before the step of forming the pattern including the pixel electrode;

and

the manufacturing method further includes a step of forming a buffering insulation layer between the step of forming the pattern including the pixel electrode and the step of forming the pattern including the active layer.

3. The manufacturing method according to claim 2, wherein after the step of forming the pattern including the active layer, the manufacturing method further includes steps of:

forming a via at a position of the buffering insulation layer corresponding to the pixel electrode; and

forming a pattern including a source and a drain, the drain being connected with the pixel electrode through the via.

4. The manufacturing method according to claim 3, wherein the manufacturing method further includes a step of:

forming a source ohmic contact layer between the source and the active layer, and forming a drain ohmic contact layer between the drain and the active layer.

5. The manufacturing method according to claim 4, wherein the step of forming the source ohmic contact layer and the drain ohmic contact layer includes:

forming a doped semiconductor material layer;

performing a first patterning process on the doped semiconductor material layer, so as to form a source-drain ohmic contact layer that covers the entire active layer; and

performing a second patterning process on the source-drain ohmic contact layer, so as to form the spaced source ohmic contact layer and drain ohmic contact layer.

6. The manufacturing method according to claim 5, wherein the step of forming the source-drain ohmic contact layer that covers the entire active layer and the step of forming the pattern including the active layer are performed through a single patterning process;

and

the step of forming the spaced source ohmic contact layer and drain ohmic contact layer and the step of forming the pattern including the source and the drain are performed through a single patterning process.

7. The manufacturing method according to claim 3, wherein after the step of forming the pattern including the source and the drain, the manufacturing method further includes a step of:

forming a passivation layer.

8. The manufacturing method according to claim 7, wherein the passivation layer and the buffering insulation layer are formed by a vapor deposition method, and at least one of a material of the passivation layer and a material of the buffering insulation layer including silicon nitride, the chamber pressure when forming the passivation layer being between 1400 mT and 1600 mT, and the chamber pressure when forming the buffering insulation layer being between 1100 mT and 1300 mT.

9. The manufacturing method according to claim 7, wherein after the step of forming the passivation layer, the manufacturing method further includes a step of:

forming a pattern including a common electrode, the common electrode including a plurality of common electrode strips.

10. An array substrate, which includes a thin film transistor and a pixel electrode, wherein the pixel electrode is located under a layer where an active layer of the thin film transistor is located, and is insulated and spaced from the active layer, the pixel electrode being electrically connected with a drain of the thin film transistor.

11. The array substrate according to claim 10, wherein a buffering insulation layer is provided between the active layer of the thin film transistor and the pixel electrode.

12. The array substrate according to claim 11, wherein a via is provided at a position of the buffering insulation layer corresponding to the pixel electrode, the drain of the thin film transistor being connected with the pixel electrode through the via.

13. The array substrate according to claim 10, wherein a source ohmic contact layer is provided between a source and the active layer of the thin film transistor, and a drain ohmic contact layer is provided between the drain and the active layer of the thin film transistor.

14. The array substrate according to claim 11, wherein a source ohmic contact layer is provided between a source and the active layer of the thin film transistor, and a drain ohmic contact layer is provided between the drain and the active layer of the thin film transistor.

15. The array substrate according to claim 11, wherein the array substrate further includes a passivation layer and a common electrode provided on the passivation layer, the common electrode including a plurality of common electrode strips, and the passivation layer covering the source and drain of the thin film transistor and the buffering insulation layer.

16. The array substrate according to claim 14, wherein at least one of a material of the buffering insulation layer and a material of the passivation layer includes silicon nitride.

17. A display device, which includes an array substrate, the array substrate including a thin film transistor and a pixel electrode, wherein the pixel electrode is located under a layer where an active layer of the thin film transistor is located, and is insulated and spaced from the active layer, the pixel electrode being electrically connected with a drain of the thin film transistor.

18. The display device according to claim 17, wherein a buffering insulation layer is provided between the active layer of the thin film transistor and the pixel electrode.

19. The display device according to claim 18, wherein a via is provided at a position of the buffering insulation layer corresponding to the pixel electrode, the drain of the thin film transistor being connected with the pixel electrode through the via.

20. The display device according to claim 17, wherein a source ohmic contact layer is provided between a source and the active layer of the thin film transistor, and a drain ohmic contact layer is provided between the drain and the active layer of the thin film transistor.