LOCALIZED AND SELF-ALIGNED PUNCH THROUGH STOPPER DOPING FOR FINFET

• US 20170012100A1
• Filed: 07/07/2015
• Published: 01/12/2017
• Est. Priority Date: 07/07/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Leobandung, Effendi, Yamashita, Tenko
• Granted Patent: US 9,698,225 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02428 Structure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.

Claims

1. A method for doping punch through stoppers (PTSs), comprising:

forming fins in a monocrystalline substrate;

forming a dielectric layer at a base portion between the fins;

forming spacers on sidewalls of the fins down to a top portion of the dielectric layer;

recessing the dielectric layer to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps;

doping the fins through the gaps to form PTSs in the fins; and

filling the gaps with a dielectric material to form a continuous dielectric layer.

2. The method as recited in claim 1, wherein the monocrystalline substrate includes Si, and the method further comprises mixing Ge in the fins to form SiGe fins.

3. The method as recited in claim 2, wherein mixing Ge in the fins to form SiGe fins includes depositing a SiGe layer on the fins and oxidizing the SiGe layer to condense Ge and diffuse the Ge into the fins.

4. The method as recited in claim 2, wherein the SiGe fins extend into the monocrystalline substrate below the dielectric layer.

5. The method as recited in claim 1, wherein doping the fins includes plasma doping sides of the fins through the gaps.

6. The method as recited in claim 1, further comprising annealing the PTSs to activate the PTSs.

7. The method as recited in claim 1, further comprising etching back the continuous dielectric layer to a position on the spacers.

8. The method as recited in claim 7, further comprising removing the spacers to expose a channel portion of the fin above the PTSs.

9. The method as recited in claim 7, further comprising recessing the spacers down to the dielectric layer to expose a channel portion of the fin above the PTSs.

10. A method for doping punch through stoppers (PTSs), comprising:

forming fins in a monocrystalline Si substrate;

forming a dielectric layer at a base portion between the fins;

mixing Ge in the fins to form SiGe fins, wherein the SiGe fins extend into the monocrystalline Si substrate below the dielectric layer;

forming spacers on sidewalls of the SiGe fins down to a top portion of the dielectric layer;

recessing the dielectric layer to form self-aligned gaps between the top portion of the dielectric layer and the spacer to expose the SiGe fins in the gaps;

plasma doping the fins through the gaps to form PTSs in the SiGe fins;

activating the PTSs by annealing;

filling the gaps with a dielectric material to form a continuous dielectric layer; and

etching back the dielectric layer to a position on the spacers.

11. The method as recited in claim 10, wherein mixing Ge in the fins to form SiGe fins includes depositing a SiGe layer on the fins and oxidizing the SiGe layer to condense Ge and diffuse the Ge into the fins.

12. The method as recited in claim 10, further comprising removing the spacers to expose a channel portion of the fin above the PTSs.

13. The method as recited in claim 10, further comprising recessing the spacers down to the dielectric layer to expose a channel portion of the fin above the PTSs.

14. The method as recited in claim 10, wherein the SiGe fins include a channel portion on a first side of the PTS and a second portion on a second side of the PTS formed in the substrate.

15. The method as recited in claim 14, wherein the channel portion includes a p-type fin field effect transistor channel and the plasma doping includes n-type dopants.

16. A fin device having a punch through stopper (PTS), comprising:

a fin disposed between source and drain regions and adjacent to a gate structure;

the fin including a SiGe fin formed into a monocrystalline Si substrate, the SiGe fin having a portion extending above a top surface of the substrate and a second portion buried below the top surface of the substrate; and

the portion extending above the top surface of the substrate including a first region forming a transistor channel, a second region forming a PTS and a third portion between the top portion of the substrate and the PTS.

17. The device as recited in claim 16, wherein the PTS region is between 10 nm and 50 nm in thickness.

18. The device as recited in claim 16, wherein the device includes a p-type fin field effect transistor.

19. The device as recited in claim 18, wherein the PTS region includes n-type dopants having a concentration of between about 1×

10¹⁷ and 1×

10²⁰ cm<sup>−

3</sup>.

20. The device as recited in claim 16, wherein the gate structure includes a gate dielectric and gate conductor formed on top of the fin.