INCREASED CONTACT AREA FOR FINFETS

• US 20170012129A1
• Filed: 07/09/2015
• Published: 01/12/2017
• Est. Priority Date: 07/09/2015
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Basker, Veeraraghavan S., Lin, Chung-Hsun, Liu, Zuoguang, Yamashita, Tenko, Yeh, Chun-Chen
• Granted Patent: US 9,680,020 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess.

Claims

1. A method for forming fin field effect transistors, comprising:

epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section;

forming a dielectric liner over the S/D regions;

etching a dielectric fill formed over the S/D regions to expose a top portion of the diamond-shaped cross section;

recessing the fins into the diamond-shaped cross section;

exposing an outer surface of the diamond-shaped cross section of the S/D regions;

forming a contact liner on the exposed outer surface of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed; and

forming contacts over surfaces of the top portion and in the recess.

2. The method as recited in claim 1, wherein etching the dielectric fill includes performing a timed etch in accordance with a pattern to reach the top portion of the diamond-shaped cross section.

3. The method as recited in claim 1, wherein recessing the fins into the diamond-shaped cross section includes performing a selective etch to etch a portion of the fins within the diamond-shaped cross section.

4. The method as recited in claim 3, wherein performing the selective etch includes performing a reactive ion etch with an HBr chemistry.

5. The method as recited in claim 1, further comprising forming gate structures on the fins.

6. The method as recited in claim 5, wherein forming the gate structures on the fins includes constructing a replacement metal gate structure.

7. The method as recited in claim 1, wherein exposing the outer surface of the diamond-shaped cross section of the S/D regions includes etching away the dielectric liner from the outer surface.

8. The method as recited in claim 1, wherein forming contacts over surfaces of the top portion and in the recess includes forming the contacts over at least the outer surfaces of the diamond-shaped cross section of the S/D regions, and on exposed sidewalls in the recess where the fins were recessed.

9. The method as recited in claim 1, wherein the fins are recessed such that a recessed fin height is less than 30% of an original fin height.

10. A method for forming fin field effect transistors, comprising:

forming fins from a silicon layer of a silicon-on-insulator substrate;

forming a dummy gate structure on the fins;

epitaxially growing source and drain (SID) regions on the fins, the S/D regions including a diamond-shaped cross section;

forming a dielectric liner over the S/D regions;

depositing a dielectric fill over the dummy gate structure and the S/D regions;

replacing the dummy gate with a replacement metal gate structure and recessing the replacement metal gate structure;

etching the dielectric fill over the S/D regions to expose a top portion of the diamond-shaped cross section;

recessing the fins into the diamond-shaped cross section;

exposing an outer surface of the diamond-shaped cross section of the S/D regions;

forming a contact liner on the exposed outer surface of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed; and

forming contacts over surfaces of the top portion and in the recess.

11. The method as recited in claim 10, wherein etching the dielectric fill includes performing a timed etch in accordance with a pattern to reach the top portion of the diamond-shaped cross section.

12. The method as recited in claim 10, wherein recessing the fins into the diamond-shaped cross section includes performing a selective etch to etch a portion of the fins within the diamond-shaped cross section.

13. The method as recited in claim 12, wherein performing the selective etch includes performing a reactive ion etch with an HBr chemistry.

14. The method as recited in claim 10, wherein exposing the outer surface of the diamond-shaped cross section of the S/D regions includes etching away the dielectric liner from the outer surface.

15. The method as recited in claim 10, wherein forming contacts over surfaces of the top portion and in the recess includes forming the contacts over at least the outer surfaces of the diamond-shaped cross section of the S/D regions, and on exposed sidewalls in the recess where the fins were recessed.

16. The method as recited in claim 10, wherein the fins are recessed such that a recessed fin height is less than 30% of an original fin height.

17. A fin field effect transistor, comprising:

a gate structure formed on a fin;

epitaxially grown source and drain (S/D) regions formed on the fin adjacent to the gate structure, the S/D regions including a diamond-shaped cross section wherein the diamond-shaped cross section includes;

internal sidewalls where the fin was recessed to a reduced height, and

an external top portion of the diamond-shaped cross section of the S/D regions; and

a contact liner formed over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions; and

contacts formed over the contact liner and over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions.

18. The transistor as recited in claim 17, wherein the fin is recessed least one half a fin height.

19. The transistor as recited in claim 17, wherein a dielectric liner covers at least a bottom portion of the diamond-shaped cross section of the S/D regions.

20. The transistor as recited in claim 17, wherein the S/D regions include unmerged epitaxial S/D regions.