SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20170012136A1
• Filed: 07/05/2016
• Published: 01/12/2017
• Est. Priority Date: 07/07/2015
• Status: Abandoned Application

• Current Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Maegawa, Yosuke, Soejima, Narumasa, Miyahara, Shinichiro
• Application Number:
  US15/201,938
• Publication Number:
  US 20170012136A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

Abstract

A terminal structure includes: a first trench extending along a depth direction from an upper surface of a semiconductor substrate; a plurality of second trenches, each of which extends along the depth direction from a bottom surface of the first trench and which are arranged at intervals in a direction away from an element portion; a plurality of first floating regions having a floating potential, each of which is exposed at the bottom surface of the first trench, is disposed between the second trenches, and forms a PN-junction with a surrounding region thereof; and a plurality of second floating regions having a floating potential, each of which is exposed at a bottom surface of the second trench and forms a PN-junction with a surrounding region thereof. The plurality of second floating regions is arranged to be separated from each other in the direction away from the element portion.

Claims

1. A semiconductor device comprising:

a semiconductor substrate partitioned into an element portion provided with a switching structure and a peripheral portion provided with a terminal structure,

wherein the terminal structure includes;

a first trench extending along a depth direction from one of main surfaces of the semiconductor substrate;

a plurality of second trenches, wherein each of the second trenches extends along the depth direction from a bottom surface of the first trench, and the second trenches are arranged at intervals in a direction away from the element portion;

a plurality of first floating regions having a floating potential, wherein each of the first floating regions is disposed at the bottom surface of the first trench, is arranged between the second trenches, and forms a PN-junction with a surrounding region thereof; and

a plurality of second floating regions having a floating potential, wherein each of the second floating regions is disposed at a bottom surface of the second trench and forms a PN-junction with a surrounding region thereof, and

the second floating regions are arranged to be separated from each other in the direction away from the element portion.

2. The semiconductor device according to claim 1, wherein

the first floating region and the second floating region are arranged to be separated from each other in the depth direction.

3. The semiconductor device according to claim 1, wherein

in a view along a direction orthogonal to the one of main surfaces of the semiconductor substrate, a part of each of the second floating regions is arranged to overlap the first floating region.

4. A manufacturing method of a semiconductor device comprising a semiconductor substrate partitioned into an element portion provided with a switching structure and a peripheral portion provided with a terminal structure, the method comprising:

preparing the semiconductor substrate;

forming a first trench extending along a depth direction from one of main surfaces of the semiconductor substrate at the peripheral portion;

forming a plurality of second trenches, wherein each of second trenches extends along the depth direction from a bottom surface of the first trench and second trenches are arranged at intervals in a direction away from the element portion;

forming a plurality of first floating regions having a floating potential, wherein each of first floating regions is disposed at the bottom surface of the first trench, is arranged between the second trenches, and forms PN-junction with a surrounding region thereof; and

forming a plurality of second floating regions having a floating potential, wherein each of the second floating regions is disposed at a bottom surface of the second trench and forms a PN-junction with a surrounding region thereof, and

the second floating regions are arranged to be separated from each other in the direction away from the element portion.

5. The manufacturing method according to claim 4, wherein

the forming of the plurality of first floating regions and the forming of the plurality of second floating regions are performed at the same time by implanting ions toward bottom surfaces of the first and second trenches in a state where the first and second trenches are exposed.

6. The manufacturing method according to claim 4, wherein

in the preparing of the semiconductor substrate, the semiconductor substrate is prepared to include at the peripheral portion a configuration in that a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type are laminated, the second semiconductor layer being exposed at the one of main surfaces of the semiconductor substrate,

in the forming of the first trench, the first trench which is shallower than the second semiconductor layer is formed, and

the forming of the plurality of second trenches and the forming of the plurality of first floating regions are performed at the same time by forming the plurality of second trenches extending along the depth direction from the bottom surface of the first trench.