SEMICONDUCTOR MEMORY DEVICE AND I/O CONTROL CIRCUIT THEREFOR

• US 20170018294A1
• Filed: 09/30/2016
• Published: 01/19/2017
• Est. Priority Date: 11/29/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: SONG, Choung Ki
• Granted Patent: US 9,916,879 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An I/O control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.

Claims

1. A semiconductor memory device, comprising:

a mode control unit configured to generate an output signal in response to a first control signal enable signal, a second control signal enable signal, a third control signal enable signal, a fourth control signal enable signal, and a buffer enable signal received from an I/O control circuit;

a pad unit comprising an I/O mode control pad, a data I/O pad, and a data I/O strobe pad;

an input driving unit configured to be driven in response to the output signal of the mode control unit and electrically coupled to the pad unit;

an output driving unit configured to be driven in response to the output signal of the mode control unit and electrically coupled to the pad unit; and

an I/O conversion unit configured to provide a memory region with data received from the input driving unit and to provide the output driving unit with data received from the memory region in response to the fourth control signal enable signal.

2. The semiconductor memory device of claim 1, wherein the I/O control circuit comprises:

a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes;

a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal; and

a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.

3. The semiconductor memory device of claim 2, wherein:

the first control signal enable signal is a termination data strobe (TDQS) signal enable signal,

the second control signal enable signal is a data mask (WDM) signal enable signal,

the third control signal enable signal is a data bus inversion (WDBI) signal enable signal in write mode, and

the fourth control signal enable signal is a data bus inversion (RDBI) signal enable signal in read mode.

4. The semiconductor memory device of claim 1, wherein the mode control unit comprises:

a first mode control circuit configured to activate an associated output signal when one of the first control signal enable signal and the fourth control signal enable signal is activated; and

a second mode control circuit configured to activate an associated output signal when one of the second control signal enable signal and the third control signal enable signal is activated and when the buffer enable signal is activated.

5. The semiconductor memory device of claim 1, wherein the I/O mode control pad receives one of a termination data strobe (TDQS) signal, a data masking signal, and a data bus inversion (DBI) signal.

6. A semiconductor memory device, comprising:

a first mode control unit configured to generate an output signal in response to a first control signal enable signal, a second control signal enable signal, a third control signal enable signal, a fourth control signal enable signal, a buffer enable signal, a first I/O option signal, and a second I/O option signal received from an I/O control circuit;

a pad unit comprising an I/O mode control pad, a data I/O pad, and a data I/O strobe pad;

an input driving unit configured to be driven in response to the output signal of the first mode control unit and electrically coupled to the pad unit;

an output driving unit configured to be driven in response to the output signal of the first mode control unit and electrically coupled to the pad unit; and

an I/O conversion unit configured to provide a memory region with data received from the input driving unit and to provide the output driving unit with data received from the memory region in response to a fourth control signal enable signal.

7. The semiconductor memory device of claim 6, wherein the I/O control circuit comprises:

a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of I/O option modes;

a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first I/O option signal and the first mode signal; and

a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second I/O option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.

8. The semiconductor memory device of claim 7, wherein the first I/O option signal and the second I/O option signal determine an I/O option mode associated with a data I/O bandwidth.

9. The semiconductor memory device of claim 7, wherein:

the first control signal enable signal is a termination data strobe (TDQS) signal enable signal,

the second control signal enable signal is a data mask (WDM) signal enable signal,

the third control signal enable signal is a data bus inversion (WDBI) signal enable signal in write mode, and

the fourth control signal enable signal is a data bus inversion (RDBI) signal enable signal in read mode.

10. The semiconductor memory device of claim 6, wherein the first mode control unit comprises:

a first mode control circuit configured to activate an associated output signal based on the activation state of the fourth control signal enable signal when the second I/O option signal is disabled and to activate the associated output signal based on the activation state of the first control signal enable signal when the first I/O option signal is enabled; and

a second mode control circuit configured to activate an associated output signal when the second I/O option signal is disabled if one of the second control signal enable signal and the third control signal enable signal is activated and the buffer enable signal is activated.

11. The semiconductor memory device of claim 6, further comprising a second mode control unit configured to activate the fourth control signal enable signal when the second I/O option signal is disabled and provide the activated fourth control signal enable signal to the I/O conversion unit.