NAND MEMORY CELL STRING HAVING A STACKED SELECT GATE STRUCTURE AND PROCESS FOR FOR FORMING SAME
First Claim
1. A memory string, comprising:
- a plurality of core cells serially connected between a source select gate and a drain select gate along a channel, each core cell including an internal wordline separated from the channel by a stack of layers including a charge trapping layer;
wherein at least one of the source and drain select gates is a stacked select gate comprising a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the plurality of core cells by the first component, and the first component comprises a first gate separated from the channel by a stack of layers including a charge trapping layer; and
wherein a distance between the first gate of the first component and the internal wordline of a first core cell in the plurality of core cells is substantially the same as distances between each internal wordline in the plurality of word core cells.
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Abstract
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.
11 Citations
20 Claims
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1. A memory string, comprising:
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a plurality of core cells serially connected between a source select gate and a drain select gate along a channel, each core cell including an internal wordline separated from the channel by a stack of layers including a charge trapping layer; wherein at least one of the source and drain select gates is a stacked select gate comprising a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the plurality of core cells by the first component, and the first component comprises a first gate separated from the channel by a stack of layers including a charge trapping layer; and wherein a distance between the first gate of the first component and the internal wordline of a first core cell in the plurality of core cells is substantially the same as distances between each internal wordline in the plurality of word core cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory string, comprising:
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a plurality of core cells serially connected between a source select gate and a drain select gate along a channel, each core cell including an internal wordline separated from the channel by a first stack of layers including a charge trapping layer comprising a nitride; at least one of the source and drain select gates is a stacked select gate comprising a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the plurality of core cells by the first component; and wherein the first component comprises a first gate separated from the channel by a second stack of layers having the same stoichiometric composition and thicknesses as the first stack of layers, and the second component comprises a second gate separated from the channel by a gate dielectric not including a charge trapping layer. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A memory string, comprising:
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a plurality of core cells serially connected between a source select gate and a drain select gate along a channel, each core cell including an internal wordline separated from the channel by a first oxide-nitride-oxide (ONO) stack including a charge trapping layer comprising a nitride; at least one of the source and drain select gates is a stacked select gate comprising a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the plurality of core cells by the first component; wherein the first component comprises a first gate separated from the channel by a second ONO stack having the same stoichiometric composition and thicknesses as the first ONO stack, and the second component comprises a second gate separated from the channel by a gate dielectric not including a charge trapping layer; and wherein the channel comprises a polysilicon cylinder extending vertically from source in a substrate to a drain overlying the substrate, and wherein the internal wordlines of the plurality of core cells are formed by alternating conducting and dielectric layers overlying the substrate and through which the channel extends. - View Dependent Claims (19, 20)
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Specification