MEMORY CONTROLLER, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD
First Claim
1. A memory controller that controls a plurality of memories individually through a communication route common to the plurality of memories, the memory controller comprising:
- a holding unit configured to hold latency information that indicates a latency of each of the plurality of memories;
a storage configured to store therein a request issued by a processor for a transmission destination memory from among the plurality of memories;
an output unit configured to output the request from the storage;
a transmitter configured to delay the request received from the output unit for a delay time based on a latency of the transmission destination memory and a latency of another memory from among the plurality of memories, and transmits the request to the transmission destination memory through the common communication route; and
a data transceiver unit configured tot transmit or receive data corresponding to the request through the common communication route after a prescribed time period has elapsed since the output unit output the request.
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Abstract
A memory controller that controls a plurality of memories individually through a communication route common to the plurality of memories, the memory controller including a holding unit that holds latency information, a storage that stores therein a request issued by a processor for a transmission destination memory from among the plurality of memories, an output unit that outputs the request from the storage, a transmitter that delays the request received from the output unit for a delay time based on a latency of the transmission destination memory and a latency of another memory from among the plurality of memories, and transmits the request to the transmission destination memory through the common communication route, and a data transceiver unit that transmits or receives data corresponding to the request through the common communication route after a prescribed time period has elapsed since the output unit output the request.
16 Citations
9 Claims
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1. A memory controller that controls a plurality of memories individually through a communication route common to the plurality of memories, the memory controller comprising:
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a holding unit configured to hold latency information that indicates a latency of each of the plurality of memories; a storage configured to store therein a request issued by a processor for a transmission destination memory from among the plurality of memories; an output unit configured to output the request from the storage; a transmitter configured to delay the request received from the output unit for a delay time based on a latency of the transmission destination memory and a latency of another memory from among the plurality of memories, and transmits the request to the transmission destination memory through the common communication route; and a data transceiver unit configured tot transmit or receive data corresponding to the request through the common communication route after a prescribed time period has elapsed since the output unit output the request. - View Dependent Claims (2, 3)
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4. An information processing device comprising:
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a plurality of memories that are connected to a common communication route; a processor; and a memory controller configured to control the plurality of memories individually through the common communication route, wherein the memory controller includes a holding unit configured to hold latency information that indicates a latency of each of the plurality of memories, a storage configured to store therein a request issued by the processor for a transmission destination memory from among the plurality of memories, an output unit configured to output the request from the storage, a transmitter configured to delay the request received from the output unit for a delay time based on a latency of the transmission destination memory and a latency of another memory from among the plurality of memories, and transmits the request to the transmission destination memory through the common communication route, and a data transceiver unit configured to transmit or receive data corresponding to the request through the common communication route after a prescribed time period has elapsed since the output unit output the request. - View Dependent Claims (5, 6)
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7. A control method for controlling an information processing device that includes a processor, a memory controller, and a plurality of memories, the method comprising:
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issuing, by the processor, a request for a transmission destination memory from among the plurality of memories; storing the request in a storage included in the memory controller; outputting, by the memory controller, the request from the storage; delaying, by the memory controller, the output request for a delay time based on a latency of the transmission destination memory and a latency of another memory from among the plurality of memories, and transmitting the output request from the memory controller to the transmission destination memory through a communication route common to the plurality of memories; and transmitting or receiving, by the memory controller, data corresponding to the request through the common communication route after a prescribed time period has elapsed since the request was output. - View Dependent Claims (8, 9)
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Specification