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MEMORY CONTROLLER, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD

  • US 20170024146A1
  • Filed: 06/13/2016
  • Published: 01/26/2017
  • Est. Priority Date: 07/23/2015
  • Status: Abandoned Application
First Claim
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1. A memory controller that controls a plurality of memories individually through a communication route common to the plurality of memories, the memory controller comprising:

  • a holding unit configured to hold latency information that indicates a latency of each of the plurality of memories;

    a storage configured to store therein a request issued by a processor for a transmission destination memory from among the plurality of memories;

    an output unit configured to output the request from the storage;

    a transmitter configured to delay the request received from the output unit for a delay time based on a latency of the transmission destination memory and a latency of another memory from among the plurality of memories, and transmits the request to the transmission destination memory through the common communication route; and

    a data transceiver unit configured tot transmit or receive data corresponding to the request through the common communication route after a prescribed time period has elapsed since the output unit output the request.

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