Method and Apparatus for Caching Flash Translation Layer (FTL) Table
First Claim
Patent Images
1. A digital processing system operable to store information, comprising:
- a non-volatile memory (“
NVM”
) organized its memory space into memory blocks for storing data persistently, each of the memory blocks divided into a plurality of physical pages addressable by corresponding physical page addresses (“
PPAs”
);
an address mapping table situated in the NVM and organized to include a plurality of entries for memory accessing to the NVM, each entry of the address mapping table addressed to a physical page of NVM; and
a random access memory (“
RAM”
) cache coupled to the NVM and configured to cache at least a portion of the address mapping table based on a table caching mechanism.
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Accused Products
Abstract
A solid-state drive (“SSD”) containing a non-volatile memory (“NVM”), flash translation layer (“FTL”) table, cache node index table, and random access memory (“RAM”) configured to cache at least a portion of the FTL table is disclosed. The NVM is organized its memory space into memory blocks for data storage wherein each of the memory blocks is further divided into a set of physical pages addressable by corresponding physical page addresses (“PPAs”). The FTL table, also known as address mapping table, includes multiple entries used for NVM memory accessing. Each entry of the FTL table stores a PPA addressing a physical page in the NVM. The RAM caches or stores a portion of the FTL table based on a table caching mechanism. The cache node index table resided in the RAM or RAM cache contains indexing information associated with the FTL table.
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Citations
20 Claims
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1. A digital processing system operable to store information, comprising:
-
a non-volatile memory (“
NVM”
) organized its memory space into memory blocks for storing data persistently, each of the memory blocks divided into a plurality of physical pages addressable by corresponding physical page addresses (“
PPAs”
);an address mapping table situated in the NVM and organized to include a plurality of entries for memory accessing to the NVM, each entry of the address mapping table addressed to a physical page of NVM; and a random access memory (“
RAM”
) cache coupled to the NVM and configured to cache at least a portion of the address mapping table based on a table caching mechanism. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A solid state drive (“
- SSD”
) operable to store information persistently, comprising;a non-volatile memory (“
NVM”
) organized its memory space into memory blocks for storing data persistently, each of the memory blocks divided into a plurality of physical pages addressable by corresponding physical page addresses (“
PPAs”
), wherein the NVM includes a flash translation layer (“
FTL”
) table containing a set of PPAs; anda random access memory (“
RAM”
) coupled to the NVM and configured to cache at least a portion of the FTL table, wherein the RAM includes a cache node index table containing index information relating to the FTL table. - View Dependent Claims (16, 17, 18)
- SSD”
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19. A method for persistently data storage, comprising:
-
receiving a read command with a logical block address (“
LBA”
) for accessing information stored in a non-volatile memory (“
NVM”
);searching a flash translation layer (“
FTL”
) index table in a random access memory (“
RAM”
) cache to identify a valid entry associated to a FTL table in response to the LBA;identifying whether cached FTL table located in FTL cache RAM in the RAM containing the valid entry in accordance with the LBA; and reading a portion of FTL table containing the valid entry from the NVM to the FTL cache RAM in the RAM. - View Dependent Claims (20)
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Specification
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Current AssigneePoint Financial, Inc.
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Original AssigneeCnex Labs, Inc.
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InventorsLuo, Shanying, Huang, Yiren Ronnie
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Application NumberUS15/217,934Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current1/1CPC Class CodesG06F 12/0246 in block erasable memory, e...G06F 12/0891 using clearing, invalidatin...G06F 12/0895 of parts of caches, e.g. di...G06F 12/1009 using page tables, e.g. pag...G06F 12/123 with age lists, e.g. queue,...G06F 2212/1044 Space efficiency improvementG06F 2212/222 Non-volatile memoryG06F 2212/608 Details relating to cache m...G06F 2212/7201 Logical to physical mapping...G06F 2212/7202 Allocation control and poli...G06F 2212/7204 Capacity control, e.g. part...G06F 2212/7205 Cleaning, compaction, garba...G06F 2212/7206 Reconfiguration of flash me...
