METHOD OF CLEANING BOTTOM OF VIA HOLE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20170025308A1
• Filed: 03/09/2016
• Published: 01/26/2017
• Est. Priority Date: 03/10/2015
• Status: Abandoned Application

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: MATSUMOTO, Kenji
• Application Number:
  US15/065,667
• Publication Number:
  US 20170025308A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: C23C 14/021 Cleaning or etching treatments
• CPC Class Codes: C23C 14/046 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 14/16 on metallic substrates or on substrates of boron or silicon
• CPC Class Codes: C23C 16/0227 by cleaning or etching
• CPC Class Codes: C23C 16/045 Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

In a method of cleaning a bottom of a via hole, a copper oxide on a surface of an underlying Cu wiring exposed at the bottom of the via hole is removed before forming a Cu wiring in a trench and the via hole extended between the trench and the underlying Cu wiring. The trench and the via hole are formed in a predetermined pattern in an interlayer insulating film of a substrate. Reducing species containing a metal in a state capable of reducing the copper oxide is supplied to the bottom of the via hole. The metal has a higher oxidation tendency than Cu and an oxide of the metal has a lower electrical resistance than the copper oxide. The copper oxide is removed by reducing the copper oxide and the oxide of the metal is generated through a reaction between the metal in the reducing species and the copper oxide.

Claims

1. A method of cleaning a bottom of a via hole, by removing a copper oxide on a surface of an underlying Cu wiring exposed at the bottom of the via hole before forming a Cu wiring in a trench and the via hole extended between the trench and the underlying Cu wiring, the trench and the via hole being formed in a predetermined pattern in an interlayer insulating film of a substrate, the method comprising:

supplying to the bottom of the via hole reducing species containing a metal, the metal which has a higher oxidation tendency than Cu and whose oxide has a lower electrical resistance than the copper oxide, in a state capable of reducing the copper oxide; and

removing the copper oxide by reducing the copper oxide and generating the oxide of the metal through a reaction between the metal contained in the reducing species and the copper oxide on the surface of the underlying Cu wiring.

2. The method of claim 1, wherein the metal is Mn, Zn, Sn or In.

3. The method of claim 1, wherein the metal is deposited as the reducing species by PVD on a surface of the substrate which includes the bottom of the via hole, and the deposited metal and the copper oxide on the surface of the underlying Cu wiring react with each other by heating.

4. The method of claim 1, wherein a film containing the metal is formed by CVD on a surface of the substrate which includes the bottom of the via hole by using a compound gas containing the metal as the reducing species, and the metal contained in the film and the copper oxide on the surface of the underlying Cu wiring react with each other.

8. The method of claim 1, wherein, before the cleaning of the bottom of the via hole, moisture is removed by performing a degas process on the substrate.

5. A method of cleaning a bottom of a via hole by removing a copper oxide on a surface of an underlying Cu wiring exposed at the bottom of the via hole before forming a Cu wiring in a trench and the via hole extended between the trench and the underlying Cu wiring, the trench and the via hole being formed in a predetermined pattern in an interlayer insulating film of a substrate, the method comprising:

supplying a Mn-containing material which contains Mn in a state capable of reducing the copper oxide to the bottom of the via hole as reducing species; and

removing the copper oxide by reducing the copper oxide and generating a manganese oxide through a reaction between the Mn-containing material and the copper oxide on the surface of the underlying Cu wiring.

6. The method of claim 5, wherein Mn is deposited as the Mn-containing material by PVD on a surface of the substrate which includes the bottom of the via hole, and the deposited Mn and the copper oxide on the surface of the underlying Cu wiring react with each other by heating.

7. The method of claim 5, wherein a manganese film is formed by CVD on a surface of the substrate which includes the bottom of the via hole by using an organic Mn compound gas as the Mn-containing material, and the manganese film and the copper oxide on the surface of the underlying Cu wiring react with each other.

9. A method of manufacturing a semiconductor device, which forms a Cu wiring connected to an underlying Cu wiring by filling a Cu-based film in a trench and the via hole extended between the trench and the underlying Cu wiring, the trench and the via hole being formed in a predetermined pattern in an interlayer insulating film of a substrate, the method comprising:

cleaning a bottom of the via hole by supplying reducing species containing a metal which has a higher oxidation tendency than Cu and whose oxide has a lower electrical resistance than a copper oxide formed on the surface of the underlying Cu wiring, in a state capable of reducing the copper oxide, and removing the copper oxide by reducing the copper oxide and generating the oxide of the metal through a reaction between the metal contained in the reducing species and the copper oxide;

forming a barrier film on a surface of the interlayer insulating film;

filling a Cu-based film in the trench and the via hole; and

forming a Cu wiring by polishing a surface of the substrate including the Cu-based film.

10. The method of claim 9, wherein in the cleaning the bottom of the via hole, the metal is Mn, Zn, Sn, or In.

11. The method of claim 9, wherein in the cleaning the bottom of the via hole, the metal is deposited as the reducing species by PVD on a surface of the substrate which includes the bottom of the via hole, and the deposited metal and the copper oxide on the surface of the underlying Cu wiring react with each other by heating.

12. The method of claim 9, wherein in the cleaning the bottom of the via hole, a film containing the metal is formed by CVD on a surface of the substrate which includes the bottom of the via hole by using a compound gas containing the metal as the reducing species, and the metal contained in the film and the copper oxide on the surface of the underlying Cu wiring react with each other.

16. The method of claim 9, wherein, before the cleaning of the bottom of the via hole, moisture is removed by performing a degas process on the substrate.

17. The method of claim 9, wherein the filling the Cu-based film in the trench and the via hole is performed by Cu plating.

18. The method of claim 9, wherein the forming the Cu-based film in the trench and the via hole is performed by PVD.

19. The method of claim 18, further comprising, before the filling the Cu-based film in the trench and the via hole, forming a layer to be wetted that is made of a metal, which is wetted by cu or cu alloy, on the surface of the barrier film,

wherein the filling the Cu-based film in the trench and the via hole is performed by PVD under a condition in which the Cu-based film is movable on the layer to be wetted.

20. The method of claim 19, wherein the layer to be wetted is made of Ru or Co.

21. The method of claim 19, wherein the layer to be wetted is formed by CVD.

13. A method of manufacturing a semiconductor device, which forms a Cu wiring connected to an underlying Cu wiring by filling a Cu-based film in a trench and a via hole extended between the trench and the underlying Cu wiring, the trench and the via hole being formed in a predetermined pattern in an interlayer insulating film of a substrate, the method comprising:

cleaning the bottom of the via hole by supplying to the bottom of the via hole a Mn-containing material which contains Mn in a state capable of reducing a copper oxide formed on the surface of the underlying Cu wiring as reducing species, and removing the copper oxide by reducing the copper oxide and generating a manganese oxide through a reaction between the Mn-containing material and the copper oxide;

forming a barrier film on the surface of the interlayer insulating film;

filling the Cu-based film in the trench and the via hole; and

forming a Cu wiring by polishing a surface of the substrate including the Cu-based film.

14. The method of manufacturing semiconductor device of claim 13, wherein in the cleaning the bottom of a via hole, a metal Mn as the Mn-containing material is deposited by PVD on the surface of the substrate which includes the bottom of a via hole, and the deposited Mn and the copper oxide on the surface of the underlying Cu wiring react with each other by heating.

15. The method of claim 13, wherein in the cleaning the bottom of the via hole, a manganese film is formed by CVD on the surface of the substrate which includes the bottom of the via hole by using an organic Mn compound gas as the Mn-containing material, and the manganese film and the copper oxide on the surface of the underlying Cu wiring react with each other.