3D FANOUT STACKING

• US 20170025380A1
• Filed: 10/20/2015
• Published: 01/26/2017
• Est. Priority Date: 07/21/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Zhai, Jun, Lai, Kwan-Yu, Hu, Kunzhong
• Granted Patent: US 11,056,373 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/182 : Disposition

Abstract

Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die.

Claims

1. A package comprising:

a first-first level die and a second-first level die arranged side-by-side;

a first row of conductive pillars protruding from a front side of the first-first level die;

a second row of conductive pillars protruding from a front side of the second-first level die;

a back side of a second level active die attached to the front side of the first-first level die and the front side of the second-first level die laterally between the first and second rows of conductive pillars; and

a redistribution layer (RDL) on and in electrical contact with the first and second rows of conductive pillars and a front side of the second level active die.

2. The package of claim 1, wherein a back side of the second level active die is attached to the first-first level die and the second-first level die with a die attach film.

3. The package of claim 1, wherein the second level active die and the first and second rows of conductive pillars are 30 μ

m-80 μ

m tall.

4. The package of claim 1, further comprising a second-second level die and a third-second level die laterally adjacent to opposite sides of the second level active die;

wherein the RDL is on an in electrical contact with front sides of the second-second level die and the third-second level die.

5. The package of claim 4, wherein the second level active die is rectangular, the first and second rows of conductive pillars are laterally adjacent to a first pair of laterally opposite sides of the second level active die, and the second-second level die and the third-second level die are laterally adjacent to a second pair of laterally opposite sides of the second level active die.

6. A package comprising:

a first level die;

a plurality of conductive pillars extending from a front side of the first level die;

a back side of a second level active die attached to the front side of the first level die; and

a redistribution layer (RDL) on and in electrical contact with the plurality of conductive pillars and a front side of the second level active die.

7. The package of claim 6, wherein the plurality of conductive pillars extend from a build-up layer of the first level die.

8. The package of claim 7, wherein the front side of the second level active die comprises a planarized front surface of a build-up layer including plurality of conductive stud surfaces, and the RDL is formed on an in electrical contact with the plurality of conductive stud surfaces of the second level active die.

9. The package of claim 7, wherein:

the first level die is encapsulated within a first level molding compound layer; and

the second level active die and the plurality of conductive pillars are encapsulated within a second level molding compound layer.

10. The package of claim 9, wherein the front side of the first level die comprises a planarized front surface of the build-up layer including plurality of conductive stud surfaces, and the plurality of conductive pillars extend from the plurality of conductive stud surfaces.

11. The package of claim 9, wherein the plurality of conductive pillars extend from a corresponding plurality of landing pads of the build-up layer of the first level die.

12. The package of claim 11, wherein the first level molding compound layer covers a back side of the first level die.

13. The package of claim 7, wherein the first level die, the second level active die, and the plurality of conductive pillars are encapsulated within a single molding compound layer.

14. The package of claim 13, wherein the plurality of conductive pillars extend from a corresponding plurality of landing pads in the build-up layer of the first level die.

15. The package of claim 8, further comprising:

a second-first level die, and a second row of conductive pillars extending from a build-up layer of the second-first level die;

wherein the plurality of conductive pillars comprises a first row of conductive pillars extending from the build-up layer of the first level die, and the first and second rows of conductive pillars are laterally adjacent to a first pair of laterally opposite sides of the second level active die;

a second-second level die and a third-second level die laterally adjacent to a second pair of laterally opposite sides of the second level active die;

wherein the RDL is formed on an in electrical contact with the plurality of conductive stud surfaces of the second level active die, a plurality of conductive stud surfaces of the second-second level die, a plurality of conductive stud surfaces of the third-second level die, the first row of conductive pillars, and the second row of conductive pillars.

16. A method of forming a package comprising:

attaching a back side of a second level active die to a front side of one or more first level die;

wherein the second level active die is laterally between a first row of conductive pillars and a second row of conductive pillars protruding from the one or more first level die;

encapsulating the second level active die, the first row of conductive pillars, and the second row of conductive pillars in a molding compound layer;

removing a thickness of the molding compound layer to expose the first row of conductive pillars, the second row of conductive pillars, and a front side of the second level active die; and

forming a redistribution layer on and in electrical connection with front side of the second level active die, the first row of conductive pillars, and the second row of conductive pillars.

17. The method of claim 16, wherein attaching the back side of the second level active die to the front side of one or more first level die comprises:

attaching a back side of a first-first level die and a back side of a second-first level die on a carrier substrate;

encapsulating the first-first level die and the second-first level in a first level molding compound layer;

grinding the first level molding compound layer to expose a first row of conductive stud surfaces of the first-first level die and a second row of conductive stud surfaces of the second-first level die; and

forming a first row of conductive pillars on the first row of conductive stud surfaces and a second row of conductive pillars on the second row of conductive stud surfaces.

18. The method of claim 16, further comprising:

attaching a first-first level die including the first row of conductive pillars to a carrier substrate, and attaching a second-first level die including the second row of conductive pillars to the carrier substrate; and

attaching the back side of the second level active die to a front side of the first-first level die and a front side of the second-first level die.

19. The method of claim 18, further comprising encapsulating first-first level die, the second-first level die, the second level active die, the first row of conductive pillars, and the second row of conductive pillars in a molding compound layer.

20. The method of claim 16, further comprising:

attaching a front side of a first-first level die and a front side of a second-first level die to a temporary carrier substrate;

encapsulating the first-first level die and the second-first level die in a first level molding compound layer;

removing the temporary carrier substrate; and

forming a first row of conductive pillars on the front side of the first-first level die, and forming a second row of conductive pillars on the front side of the second-first level die.