THREE-DIMENSIONAL JUNCTION MEMORY DEVICE AND METHOD READING THEREOF USING HOLE CURRENT DETECTION
First Claim
1. A monolithic three-dimensional memory device comprising:
- a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate; and
a memory stack structure extending through the stack and comprising a memory film and a semiconductor junction structure vertically extending through the stack substantially perpendicular to a top surface of the substrate;
wherein the semiconductor junction structure comprises a semiconductor channel portion, a lower doped semiconductor source portion having a doping of a first conductivity type, and an upper doped semiconductor drain portion having a doping of a second conductivity type such that a junction is located between the semiconductor channel portion and an upper doped semiconductor drain portion; and
wherein one of the first and second conductivity types is p-type and another of the first and second conductivity types is n-type.
1 Assignment
0 Petitions
Accused Products
Abstract
Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.
-
Citations
25 Claims
-
1. A monolithic three-dimensional memory device comprising:
-
a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate; and a memory stack structure extending through the stack and comprising a memory film and a semiconductor junction structure vertically extending through the stack substantially perpendicular to a top surface of the substrate; wherein the semiconductor junction structure comprises a semiconductor channel portion, a lower doped semiconductor source portion having a doping of a first conductivity type, and an upper doped semiconductor drain portion having a doping of a second conductivity type such that a junction is located between the semiconductor channel portion and an upper doped semiconductor drain portion; and wherein one of the first and second conductivity types is p-type and another of the first and second conductivity types is n-type. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method of manufacturing a memory device, comprising:
-
forming a stack of alternating layers comprising first material layers and second material layers over a substrate; forming a memory opening through the stack of alternating layers to a top surface of the substrate; forming a lower doped semiconductor source portion having a doping of a first conductivity type at a lower portion of the memory opening; forming a memory film on a sidewall of the memory opening; forming a semiconductor channel portion on the lower doped semiconductor portion and the memory film; and forming an upper doped semiconductor drain portion having a doping of a second conductivity type on the semiconductor portion, wherein one of the first and second conductivity types is p-type and another of the first and second conductivity types is n-type. - View Dependent Claims (10)
-
-
11. A monolithic three-dimensional memory device comprising:
-
an alternating stack of insulating layers and electrically conductive layers located over a substrate; a memory opening extending through the alternating stack and at least to a top surface of the substrate and containing a memory film therein; a set of doped semiconductor material regions each having a doping of a first conductivity type and collectively extending continuously from underneath the top surface of the substrate through the memory film to a level of a topmost layer of the alternating stack, wherein the set of doped semiconductor material regions includes a doped contact region underlying the top surface of the substrate and a doped semiconductor channel extending through the memory opening; a well contact via structure extending through the alternating stack and physically contacting a top surface of the doped contact region; and an upper semiconductor material region contacting an upper portion of the doped semiconductor channel and having a doping of a second conductivity type, wherein a p-n junction is provided between the upper semiconductor material portion and the doped semiconductor channel. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
-
Specification