THREE-DIMENSIONAL JUNCTION MEMORY DEVICE AND METHOD READING THEREOF USING HOLE CURRENT DETECTION

• US 20170025421A1
• Filed: 10/03/2016
• Published: 01/26/2017
• Est. Priority Date: 05/08/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: IKAWA, Yusuke, SAKAKIBARA, Kiyohiko
• Granted Patent: US 10,074,661 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Data stored in a plurality of charge storage elements in a three-dimensional memory device can be read with high speed by measuring a majority charge carrier current passing through a vertical semiconductor channel. A memory film is provided in a memory opening extending through an alternating stack of insulating layers and electrically conductive layers. A set of doped semiconductor material regions having a doping of a first conductivity type can collectively extend continuously from underneath a top surface of a substrate through the memory film to a level of a topmost layer of the alternating stack. A well contact via structure can contact a doped contact region, which is an element of the set of doped semiconductor material regions. A p-n junction is provided within each memory opening between the doped vertical semiconductor channel and an upper doped semiconductor region having a doping of a second conductivity type.

Claims

1. A monolithic three-dimensional memory device comprising:

a stack of alternating layers comprising insulating layers and electrically conductive layers and located over a substrate; and

a memory stack structure extending through the stack and comprising a memory film and a semiconductor junction structure vertically extending through the stack substantially perpendicular to a top surface of the substrate;

wherein the semiconductor junction structure comprises a semiconductor channel portion, a lower doped semiconductor source portion having a doping of a first conductivity type, and an upper doped semiconductor drain portion having a doping of a second conductivity type such that a junction is located between the semiconductor channel portion and an upper doped semiconductor drain portion; and

wherein one of the first and second conductivity types is p-type and another of the first and second conductivity types is n-type.

2. The monolithic three-dimensional memory device of claim 1, wherein:

the first conductivity type is p-type and the second conductivity type is n-type;

the semiconductor channel portion comprises a first polycrystalline semiconductor material containing electrical dopants of the first conductivity type;

the upper doped semiconductor drain portion comprises a second polycrystalline semiconductor material;

the lower doped semiconductor source portion comprises a single crystalline semiconductor material; and

the lower doped semiconductor source portion is in epitaxial alignment with a single crystalline lattice structure of a semiconductor material in the substrate.

3. The monolithic three-dimensional memory device of claim 2, further comprising an epitaxial material portion underlying the lower doped semiconductor source portion and having a doping of the first conductivity type at a lower dopant concentration than the lower doped semiconductor source portion.

4. The monolithic three-dimensional memory device of claim 3, wherein:

the epitaxial material portion is in epitaxial alignment with a single crystalline lattice structure of a semiconductor material in the substrate; and

the substrate comprises a doped semiconductor well contacting the epitaxial material portion and having a doping of the first conductivity type at a higher dopant concentration than a dopant concentration in the epitaxial material portion; and

the substrate comprises a first conductivity type doped semiconductor region located underneath a top surface of the substrate, contacting the doped semiconductor well, and vertically spaced from the epitaxial material portion by a region of the doped semiconductor well.

5. The monolithic three-dimensional memory device of claim 3, further comprising a dielectric spacer laterally surrounding the epitaxial material portion, wherein one of the electrically conductive layers laterally surrounds the dielectric spacer.

6. The monolithic three-dimensional memory device of claim 1, further comprising:

a trench vertically extending from a first horizontal plane including a topmost surface of the stack of alternating layers to a second horizontal plane including a bottommost surface of the stack of alternating layers; and

a trench fill dielectric material portion which completely fills the trench and contacts a sidewall of each of the electrically conductive layers.

7. The monolithic three-dimensional memory device of claim 1, wherein:

the memory stack structure is located within a memory opening extending through the stack of alternating layers;

the memory film contacts a sidewall of the memory opening; and

the memory film comprises, from outside to inside, a blocking dielectric layer, a memory material layer, and a tunneling dielectric layer.

8. The monolithic three-dimensional memory device of claim 1, wherein:

the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings located over the silicon substrate;

at least one memory cell in a first device level of the three-dimensional array of NAND strings is located over another memory cell in a second device level of the three-dimensional array of NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

9. A method of manufacturing a memory device, comprising:

forming a stack of alternating layers comprising first material layers and second material layers over a substrate;

forming a memory opening through the stack of alternating layers to a top surface of the substrate;

forming a lower doped semiconductor source portion having a doping of a first conductivity type at a lower portion of the memory opening;

forming a memory film on a sidewall of the memory opening;

forming a semiconductor channel portion on the lower doped semiconductor portion and the memory film; and

forming an upper doped semiconductor drain portion having a doping of a second conductivity type on the semiconductor portion, wherein one of the first and second conductivity types is p-type and another of the first and second conductivity types is n-type.

10. The method of claim 9, wherein:

the semiconductor channel portion comprises a doped semiconductor channel portion of the first conductivity type; and

a p-n junction is formed between the doped semiconductor channel portion and the upper doped semiconductor drain portion.

11. A monolithic three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

a memory opening extending through the alternating stack and at least to a top surface of the substrate and containing a memory film therein;

a set of doped semiconductor material regions each having a doping of a first conductivity type and collectively extending continuously from underneath the top surface of the substrate through the memory film to a level of a topmost layer of the alternating stack, wherein the set of doped semiconductor material regions includes a doped contact region underlying the top surface of the substrate and a doped semiconductor channel extending through the memory opening;

a well contact via structure extending through the alternating stack and physically contacting a top surface of the doped contact region; and

an upper semiconductor material region contacting an upper portion of the doped semiconductor channel and having a doping of a second conductivity type, wherein a p-n junction is provided between the upper semiconductor material portion and the doped semiconductor channel.

12. The monolithic three-dimensional memory device of claim 11, wherein the doped contact region comprises a single crystalline semiconductor material.

13. The monolithic three-dimensional memory device of claim 12, further comprising a semiconductor material layer located within the substrate and comprising another single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the doped contact region.

14. The monolithic three-dimensional memory device of claim 11, wherein the set of doped semiconductor material regions comprises an epitaxial pedestal including a single crystalline semiconductor material and located within a lower portion of the memory opening, wherein the doped semiconductor channel overlies the epitaxial pedestal.

15. The monolithic three-dimensional memory device of claim 14, further comprising a lower doped semiconductor portion contacting a top surface of the epitaxial pedestal and a bottom surface of the doped semiconductor channel.

16. The monolithic three-dimensional memory device of claim 15, wherein the lower doped semiconductor portion has a greater concentration of dopants of the first conductivity type than the epitaxial pedestal and the doped semiconductor channel.

17. The monolithic three-dimensional memory device of claim 15, wherein the lower doped semiconductor portion comprises another single crystalline semiconductor material in epitaxial alignment with the epitaxial pedestal.

18. The monolithic three-dimensional memory device of claim 15, wherein a sidewall of the doped semiconductor channel contacts a sidewall of the lower doped semiconductor material portion.

19. The monolithic three-dimensional memory device of claim 14, wherein the doped contact region contacts a bottom surface of the epitaxial pedestal.

20. The monolithic three-dimensional memory device of claim 14, wherein the set of doped semiconductor regions comprises a doped semiconductor well laterally surrounding the doped contact region and contacting a bottom surface of the epitaxial pedestal.

21. The monolithic three-dimensional memory device of claim 14, further comprising a dielectric spacer laterally surrounding the epitaxial material portion, wherein one of the electrically conductive layers laterally surrounds the dielectric spacer.

22. The monolithic three-dimensional memory device of claim 11, wherein:

the doped semiconductor channel comprises a polycrystalline semiconductor material; and

the p-n junction includes a cylindrical surface.

23. The monolithic three-dimensional memory device of claim 11, further comprising:

a trench vertically extending at least from a first horizontal plane including a topmost surface of the alternating stack to a second horizontal plane including the top surface of the substrate; and

a trench fill dielectric material portion which completely fills the trench and contacts a sidewall of each of the electrically conductive layers.

24. The monolithic three-dimensional memory device of claim 11, wherein:

the memory film contacts a sidewall of the memory opening; and

the memory film comprises, from outside to inside, a blocking dielectric layer, a memory material layer, and a tunneling dielectric layer.

25. The monolithic three-dimensional memory device of claim 11, wherein:

the monolithic three-dimensional memory device comprises a vertical NAND device located over the substrate;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings located over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes embodied as portions of the electrically conductive layers and having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprising at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.