THREE-DIMENSIONAL GERMANIUM-BASED SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES

• US 20170025499A1
• Filed: 10/06/2016
• Published: 01/26/2017
• Est. Priority Date: 09/27/2012
• Status: Abandoned Application

• Current Assignee: Abhijit Jayant Pethe, Annalisa Cappellani, Bruce E. Beattie, Pragyansri Pathi
• Original Assignee: Abhijit Jayant Pethe, Annalisa Cappellani, Bruce E. Beattie, Pragyansri Pathi
• Inventors: Cappellani, Annalisa, Pathi, Pragyansri, Beattie, Bruce E., Pethe, Abhijit Jayant
• Application Number:
  US15/287,621
• Publication Number:
  US 20170025499A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate;

an insulating structure disposed above the semiconductor substrate;

a semiconductor layer disposed over and directly on the insulating structure;

a semiconductor body disposed on the semiconductor layer, the semiconductor body comprising a channel region and source/drain regions on both sides of the channel region, wherein the semiconductor layer is under the source/drain regions but not under the channel region, the semiconductor layer comprising a semiconductor material different from the semiconductor body; and

a gate electrode stack surrounding the channel region with a portion disposed on the insulating structure directly below the channel region, and laterally adjacent to the semiconductor layer.

2. The semiconductor structure of claim 1, wherein the insulating structure comprises a global insulating layer.

3. The semiconductor structure of claim 1, wherein the insulating structure comprises one or more isolation pedestals.

4. The semiconductor structure of claim 1, wherein the semiconductor body comprises greater than approximately 70% germanium.

5. The semiconductor structure of claim 1, further comprising:

a pair of insulating spacers, one spacer disposed between the gate electrode and the source region, and the other spacer disposed between the gate electrode and the drain region, wherein the semiconductor layer extends underneath each of the pair of spacers.

6. The semiconductor structure of claim 1, further comprising:

a pair of conducting contacts, one contact disposed on and partially surrounding the source region, and the other contact disposed on and partially surrounding the drain region.

7. The semiconductor structure of claim 1, further comprising:

one or more nanowires disposed in a vertical arrangement above the semiconductor body, wherein the gate electrode stack surrounds a channel region of each of the one or more nanowires.

8. The semiconductor structure of claim 1, wherein the gate electrode stack comprises a high-k gate dielectric layer and a metal gate electrode.

9. A semiconductor structure, comprising:

a semiconductor substrate;

an insulating structure disposed above the semiconductor substrate;

a semiconductor layer disposed over and directly on the insulating structure;

a semiconductor body disposed on the semiconductor layer, the semiconductor body comprising a channel region and source/drain regions on both sides of the channel region, wherein the semiconductor layer is under the channel region but not under the source/drain regions, the semiconductor layer comprising a semiconductor material different from the semiconductor body;

a gate electrode stack partially surrounding the channel region; and

a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the insulating structure directly below the channel region, and laterally adjacent to the semiconductor layer.

10. The semiconductor structure of claim 9, wherein the insulating structure comprises a global insulating layer.

11. The semiconductor structure of claim 9, wherein the insulating structure comprises one or more isolation pedestals.

12. The semiconductor structure of claim 9, wherein the semiconductor body comprises greater than approximately 70% germanium.

13. The semiconductor structure of claim 9, further comprising:

a pair of insulating spacers, one spacer disposed between the gate electrode and the source region, and the other spacer disposed between the gate electrode and the drain region, wherein the semiconductor layer extends underneath each of the pair of spacers.

14. The semiconductor structure of claim 9, further comprising:

one or more nanowires disposed in a vertical arrangement above the semiconductor body, wherein the gate electrode stack surrounds a channel region of each of the one or more nanowires.

15. The semiconductor structure of claim 9, wherein the gate electrode stack comprises a high-k gate dielectric layer and a metal gate electrode.

16. A semiconductor structure, comprising:

a semiconductor substrate;

an insulating structure disposed above the semiconductor substrate;

a semiconductor layer disposed over and directly on the insulating structure;

a semiconductor body disposed on the semiconductor layer, the semiconductor body comprising a channel region and source/drain regions on either side of the channel region, wherein the semiconductor layer is not under the channel region and not under the source/drain regions, the semiconductor layer comprising a semiconductor material different from the semiconductor body;

a gate electrode stack surrounding the channel region with a portion disposed on the insulating structure directly below the channel region;

a pair of conducting contacts, one contact disposed on and surrounding the source region, and the other contact disposed on and surrounding the drain region, wherein a portion of each of the pair of contacts is disposed on the insulating structure; and

a pair of insulating spacers, one spacer disposed between the gate electrode and the source region, and the other spacer disposed between the gate electrode and the drain region, wherein the semiconductor layer is disposed underneath each of the pair of spacers and laterally adjacent to a portion of the gate electrode stack and a portion of each of the conducting contacts.

17. The semiconductor structure of claim 16, wherein the insulating structure comprises a global insulating layer.

18. The semiconductor structure of claim 16, wherein the insulating structure comprises one or more isolation pedestals.

19. The semiconductor structure of claim 16, further comprising:

one or more nanowires disposed in a vertical arrangement above the semiconductor body, wherein the gate electrode stack surrounds a channel region of each of the one or more nanowires.

20. The semiconductor structure of claim 16, wherein the gate electrode stack comprises a high-k gate dielectric layer and a metal gate electrode.