Semiconductor Device and Manufacturing Method Thereof

• US 20170025548A1
• Filed: 07/19/2016
• Published: 01/26/2017
• Est. Priority Date: 07/24/2015
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 11,189,736 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07758 arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H04W 88/02 Terminal devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. The semiconductor device includes an oxide semiconductor; a second insulator; a first conductor and a first insulator that are embedded in the second insulator; a second conductor; a third conductor; and a third insulator covering the oxide semiconductor. The oxide semiconductor includes a region where an angle formed between a plane that is parallel to a bottom surface of the oxide semiconductor and the side surface of the oxide semiconductor is greater than or equal to 30° and less than or equal to 60°.

Claims

1. A semiconductor device comprising:

an oxide semiconductor;

a first conductor;

a second conductor;

a third conductor;

a first insulator;

a second insulator; and

a third insulator,

wherein the first conductor comprises a region where the first conductor and the oxide semiconductor overlap with each other with the first insulator and the third insulator positioned between the first conductor and the oxide semiconductor,

wherein the second insulator comprises an opening,

wherein the first insulator comprises a region in contact with a side surface of the second insulator in the opening,

wherein the first conductor comprises a region facing the side surface of the second insulator with the first insulator positioned between the first conductor and the second insulator,

wherein the oxide semiconductor comprises a region where a side surface and a top surface of the oxide semiconductor are in contact with the third insulator,

wherein the third insulator comprises a region where a top surface of the third insulator is in contact with the second conductor and a region where the top surface of the third insulator is in contact with the third conductor, and

wherein the oxide semiconductor comprises a region where an angle forined between a plane that is parallel to a bottom surface of the oxide semiconductor and the side surface of the oxide semiconductor is greater than or equal to 30° and

less than or equal to 60°

.

2. The semiconductor device according to claim 1,

wherein the second conductor comprises a first conductor layer that is in contact with the second insulator and a second conductor layer that is not in contact with the second insulator, and

wherein the first conductor layer is less likely to transmit oxygen than the second conductor layer.

3. The semiconductor device according to claim 1,

wherein the third conductor comprises a third conductor layer that is in contact with the second insulator and a fourth conductor layer that is not in contact with the second insulator, and

wherein the third conductor layer is less likely to transmit oxygen than the fourth conductor layer.

4. The semiconductor device according to claim 1, wherein the third insulator comprises at least one of main component elements of the oxide semiconductor other than oxygen.

5. The semiconductor device according to claim 1,

further comprising a fourth insulator comprising a region overlapping with the oxide semiconductor,

wherein the fourth insulator comprises at least one of main component elements of the oxide semiconductor other than oxygen.

6. The semiconductor device according to claim 1,

further comprising a transistor,

wherein the first conductor comprises a region functioning as a gate electrode of the transistor, and

wherein a line width of the gate electrode of the transistor is greater than or equal to 3 nm and less than or equal to 60 nm.

7. The semiconductor device according to claim 1, comprising a region where a distance between an end portion of the second conductor and an end portion of the third conductor that face each other is greater than or equal to 5 nm and less than or equal to 80 nm.

8. A semiconductor device comprising:

a first oxide semiconductor layer;

a second oxide semiconductor layer covering the first oxide semiconductor layer;

a gate insulating layer over the second oxide semiconductor layer; and

a gate electrode over the gate insulating layer,

wherein a side surface of the first oxide semiconductor layer has a taper angle greater than or equal to 30° and

less than or equal to 60°

, and

wherein the second oxide semiconductor layer is in contact with a top surface and the side surface of the first oxide semiconductor layer.

9. The semiconductor device according to claim 8,

wherein a line width of the gate electrode is greater than or equal to 3 mn and less than or equal to 60 nm.

10. A method for manufacturing a semiconductor device comprising the steps of:

forming a second insulator over a first insulator;

forming an oxide semiconductor over the second insulator;

forming a first conductor over the oxide semiconductor;

forming a first resist mask over the first conductor by a lithography method;

etching the first conductor using the first resist mask as an etching mask;

etching the oxide semiconductor and the second insulator using the first resist mask and the first conductor as etching masks so that the oxide semiconductor and the second insulator comprise regions where a taper angle of the oxide semiconductor and a taper angle of the second insulator are each greater than or equal to 30° and

less than or equal to 60°

;

removing the first resist mask and the first conductor;

forming a third insulator over the first insulator, the second insulator, and the oxide semiconductor;

performing treatment using plasma comprising oxygen on the third insulator, so that oxygen in the plasma is added to the third insulator as excess oxygen;

performing heat treatment, so that the excess oxygen in the third insulator moves to the oxide semiconductor;

forining a second conductor over the third insulator;

forming a second resist mask over the second conductor by a lithography method;

etching the second conductor and the third insulator using the second resist mask as an etching mask;

forming a fourth insulator over the first insulator and the second conductor;

forming, in the fourth insulator, an opening that exposes the second conductor;

forming, in the second conductor, an opening that exposes the third insulator, so that the second conductor is divided into a first conductor layer and a second conductor layer;

foiming a fifth insulator over the fourth insulator and the third insulator;

forming a third conductor over the fifth insulator; and

polishing the third conductor and the fifth insulator, so that the fourth insulator is exposed,

wherein the second insulator and the third insulator comprise at least one of main component elements of the oxide semiconductor other than oxygen.