EFFICIENT INTEGRATED SWITCHING VOLTAGE REGULATION

• US 20170031419A1
• Filed: 10/11/2016
• Published: 02/02/2017
• Est. Priority Date: 06/29/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sizikov, Gregory, Zelikson, Michael, Rotem, Efraim, Fayneh, Eyal
• Granted Patent: US 10,203,742 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 3/08 wherein the variable is dc
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.

Claims

1. An integrated circuit comprising:

a switching voltage regulator (SVR) comprising one or more bridge drivers to provide regulated power supply to a plurality of power domains that comprise a first power domain and a second power domain, wherein the SVR is operable to provide a plurality of switching frequencies including a first switching frequency and a second switching frequency; and

a power control unit (PCU) operable to adjust the switching frequencies of the SVR according to states of the plurality of power domains, wherein at least one of a drive strength and an active phase count of the one or more bridge drivers is adjusted by a logic unit of the SVR when at least one of the switching frequencies of the SVR is adjusted, wherein the first power domain is optimized using the first switching frequency and the second power domain is optimized using the second switching frequency.

2. The integrated circuit of claim 1 further comprises a memory unit to store the plurality of switching frequencies for the plurality of power domains.

3. The integrated circuit of claim 1, wherein the PCU is operable to access the memory unit when a state of any one of the states of the plurality of power domains changes.

4. The integrated circuit of claim 1, wherein the memory unit is part of the PCU.

5. The integrated circuit of claim 1, wherein the memory unit is accessible by software or hardware to adjust values of the switching frequencies for the plurality of power domains.

6. The integrated circuit of claim 1, wherein the power domains are associated with different parts of the integrated circuit including at least one of:

one or more processing cores,

one or more cache units,

one or more input-output (I/O) drivers, or

one or more graphics units.

7. The integrated circuit of claim 1, wherein the voltage regulator is a DC-DC buck type multiphase converter.

8. The integrated circuit of claim 1, wherein the states include P-states and C-states associated with the plurality of power domains.

9. The integrated circuit of claim 1 further comprises a memory unit to store the plurality of switching frequencies associated with P-states and switching frequencies associated with C-states.

10. The integrated circuit of claim 1, wherein the PCU is operable to adjust the switching frequencies to cause the SVR to operate with substantially minimum SVR losses.

11. The integrated circuit of claim 1, wherein the PCU is operable to adjust switching frequencies of the SVR by dynamically selecting an output signal having multiple phases from a divider of the SVR.

12. The integrated circuit of claim 1, wherein the one or more bridge drivers comprise one or more transistors that act as switches of the SVR.

13. The integrated circuit of claim 1, wherein the one or more bridge drivers of the SVR have adjustable drive strengths which are adjusted when any state of the plurality of power domains changes.

14. The integrated circuit of claim 1, wherein the logic unit to adjust drive strengths of the one or more bridge drivers to cause the SVR to operate with substantially minimum SVR losses.

15. A computer system comprising:

a memory;

a processor coupled to the memory, the processor comprising

a switching voltage regulator (SVR)-comprising one or more bridge drivers to provide regulated power supply to a plurality of power domains that comprise a first power domain and a second power domain, wherein the SVR is operable to provide a plurality of switching frequencies including a first switching frequency and a second switching frequency; and

a power control unit (PCU) operable to adjust the switching frequencies of the SVR according to states of the plurality of power domains, wherein at least one of a drive strength and an active phase count of the one or more bridge drivers is adjusted by a logic unit of the SVR when at least one of the switching frequencies of the SVR is adjusted, wherein the first power domain is optimized using the first switching frequency and the second power domain is optimized using the second switching frequency; and

a wireless interface for communicatively coupling the processor with other devices.

16. The computer system of claim 15, wherein the processor includes a plurality of processing cores, each processing core associated with a power domain from the plurality of power domains.

17. The computer system of claim 15, further comprises a display unit communicatively coupled to the processor.

18. The computer system of claim 15, wherein the memory is to store the plurality of switching frequencies for the plurality of power domains.

19. The computer system of claim 15, wherein the power domains are associated with different parts of the integrated circuit including at least one of:

one or more processing cores,

one or more cache units,

one or more input-output (I/O) drivers, or

one or more graphics units.

20. The computer system of claim 15, wherein the one or more bridge drivers comprise one or more transistors that act as switches of the SVR.