ELEMENT SIZE INCREASING INSTRUCTION

• US 20170031682A1
• Filed: 07/31/2015
• Published: 02/02/2017
• Est. Priority Date: 07/31/2015
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: EAPEN, Jacob, EYOLE, Mbou, HOSIE, Simon
• Granted Patent: US 9,965,275 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask

Abstract

An apparatus comprises processing circuitry to generate a result vector including at least one N-bit data element in response to an element size increasing instruction identifying at least a first input vector including M-bit data elements, where N>M. First and second forms of the element size increasing instruction are provided for generating the result vector using first and second subsets of data elements of the first input vector respectively. Positions of the first and second subsets of data elements in the first input vector are interleaved.

Claims

1. An apparatus comprising:

processing circuitry to generate a result vector comprising a plurality of result data elements in response to an element size increasing instruction identifying at least a first input vector comprising a plurality of M-bit data elements, where the result data elements comprise at least one N-bit data element, where N>

M;

wherein in response to a first form of the element size increasing instruction, the processing circuitry is configured to generate the result vector using a first subset of data elements of the first input vector;

in response to a second form of the element size increasing instruction, the processing circuitry is configured to generate the result vector using a second subset of data elements of the first input vector; and

positions of the first subset of data elements in the first input vector are interleaved with positions of the second subset of data elements in the first input vector.

2. The apparatus according to claim 1, wherein in response to the element size increasing instruction, the processing circuitry is configured to generate a given N-bit data element of the result vector in dependence on a corresponding M-bit data element of the first input vector selected in dependence on which form of the element size increasing instruction is processed by the processing circuitry.

3. The apparatus according to claim 1, wherein each N-bit data element of the result vector corresponds to a group of M-bit data elements of the first input vector, the group comprising one M-bit data element from each of the first and second subsets, and bit positions of the N-bit data element within the result vector are coincident with bit positions of the corresponding group of M-bit data elements in the first input vector;

and

the processing circuitry is configured to generate a given N-bit data element of the result vector in dependence on one of the corresponding group of M-bit data elements selected in dependence on which form of the element size increasing instruction is processed by the processing circuitry.

4. The apparatus according to claim 1, wherein the processing circuitry is configured to generate the result vector in dependence on a mask comprising a plurality of mask values for indicating which of the M-bit data elements of the first input vector are active data elements.

5. The apparatus according to claim 4, wherein in response to the first form of the element size increasing instruction, the processing circuitry is configured to generate the result vector using the first subset of data elements and a first subset of the mask values;

in response to the second form of the element size increasing instruction, the processing circuitry is configured to generate the result vector using the second subset of data elements and a second subset of the mask values; and

positions of the first and second subsets of the mask values are interleaved in the mask.

6. The apparatus according to claim 4, wherein in response to both the first and second forms of the element size increasing instruction, the processing circuitry is configured to generate the result vector using a first subset of the mask values.

7. The apparatus according to claim 1, wherein N=2M;

the first subset of data elements comprises even-numbered data elements of the first input vector; and

the second subset of data elements comprises odd-numbered data elements of the first input vector.

8. The apparatus according to claim 1, wherein N=4M;

in response to a third form of the element size increasing instruction, the processing circuitry is configured to generate the result vector using a third subset of data elements of the first input vector;

in response to a fourth form of the element size increasing instruction, the processing circuitry is configured to generate the result vector using a fourth subset of data elements of the first input vector; and

positions of the first, second, third and fourth subsets of data elements in the first input vector are interleaved.

9. The apparatus according to claim 1, wherein N=8M;

in response to third to eighth forms of the element size increasing instruction, the processing circuitry is configured to generate the result vector using third to eight subsets of data elements of the first input vector respectively; and

positions of the first to eighth subsets of data elements in the first input vector are interleaved.

10. The apparatus according to claim 2, wherein each M-bit data element of the first input vector is associated with a mask value indicating whether the M-bit data element is active or inactive, and

for each N-bit data element of the result vector:

when the corresponding M-bit data element of the first input vector is active, the processing circuitry is configured to generate the N-bit data element in dependence on a result of a predetermined operation applied to the corresponding M-bit data element; and

when the corresponding M-bit data element is inactive, the processing circuitry is configured to generate the N-bit data element with a value independent of the result of the predetermined operation applied to the M-bit data element.

11. The apparatus according to claim 1, wherein the result vector comprises at least one J-bit data element, where J<

N.

12. The apparatus according to claim 11, wherein the processing circuitry is configured to generate said J-bit data element with a value corresponding to a J-bit portion of an N-bit result of performing a predetermined processing operation using a corresponding M-bit data element of the first input vector.

13. The apparatus according to claim 2, wherein the processing circuitry is configured to generate the given N-bit data element of the result vector by performing a predetermined operation using the corresponding M-bit data element of the first input vector.

14. The apparatus according to claim 13, wherein the predetermined operation comprises a conversion operation to change the precision of the value represented by the corresponding M-bit data element from M bits to N bits.

15. The apparatus according to claim 13, wherein the result of the predetermined operation is dependent on the corresponding M-bit data element of the first input vector and a corresponding M-bit data element of at least one further input vector specified by the element size increasing instruction.

16. The apparatus according to claim 15, wherein the processing circuitry is configured to select the corresponding M-bit data element of the second input vector in dependence on which form of the element size increasing instruction is processed by the processing circuitry.

17. The apparatus according to claim 13, wherein the result of the predetermined operation is dependent on the corresponding M-bit data element of the first input vector and a corresponding N-bit data element of at least one further input vector specified by the element size increasing instruction.

18. The apparatus according to claim 1, wherein the first and second forms of the element size increasing instruction have different opcodes.

19. The apparatus according to claim 1, wherein the first and second forms of the element size increasing instruction have the same opcode, and the element size increasing instruction includes a field identifying whether the instruction is of the first form or the second form.

22. A computer program stored on a computer readable storage medium that, when executed by a data processing apparatus, provides a virtual machine which provides an instruction execution environment corresponding to the apparatus of claim 1.

20. An apparatus comprising:

means for generating a result vector comprising a plurality of result data elements in response to an element size increasing instruction identifying at least a first input vector comprising a plurality of M-bit data elements, where the result data elements comprise at least one N-bit data element, where N>

M;

wherein in response to a first form of the element size increasing instruction, the means for generating is configured to generate the result vector using a first subset of data elements of the first input vector;

in response to a second form of the element size increasing instruction, the means for generating is configured to generate the result vector using a second subset of data elements of the first input vector; and

positions of the first subset of data elements in the first input vector are interleaved with positions of the second subset of data elements in the first input vector.

21. A data processing method comprising:

in response to an element size increasing instruction identifying at least a first input vector comprising a plurality of M-bit data elements, generating a result vector comprising a plurality of result data elements, where the result data elements comprise at least one N-bit data element, where N>

M;

wherein in response to a first form of the element size increasing instruction, the result vector is generated using a first subset of data elements of the first input vector;

in response to a second form of the element size increasing instruction, the result vector is generated using a second subset of data elements of the first input vector; and

positions of the first subset of data elements in the first input vector are interleaved with positions of the second subset of data elements in the first input vector.