SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

• US 20170033195A1
• Filed: 02/25/2015
• Published: 02/02/2017
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: IKEDA, Tomoharu, TASBIR, Rahman MD., ONISHI, Toru, OKI, Shuhei
• Granted Patent: US 10,319,831 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.

Claims

1. A manufacturing method of a semiconductor device, the method comprising:

forming a trench in a front surface of a semiconductor substrate;

forming a gate insulating film covering an inner surface of the trench;

depositing a first fill material on a side surface of the gate insulating film in the trench;

depositing a second fill material having a higher etching resistance than the first fill material on a side surface of the first fill material in the trench;

removing a part of the first fill material in the trench and a part of the second fill material in the trench by etching from a front surface side of the semiconductor substrate so as to position a front surface of the second fill material in the trench at a shallower position than a front surface of the first fill material in the trench; and

forming a diffusion layer after the etching by an ion implantation to the semiconductor substrate from the front surface side of the semiconductor substrate.

2. The manufacturing method as in claim 1, wherein

the first fill material is polysilicon,

the second fill material is polysilicon, and

the first fill material contains a higher density of phosphorous than the second fill material.

3. The manufacturing method as in claim 1, wherein

in a width direction of the trench, a total widthwise thickness of the first fill material positioned on both sides of the second fill material is larger than a widthwise thickness of the second fill material.

4. The manufacturing method as in claim 1, wherein

the etching is performed such that a part of the front surface of the first fill material which is in contact with the gate insulating film is located at a depth within 400 nm from the front surface of the semiconductor substrate.

5. The manufacturing method as in claim 1, wherein

the semiconductor substrate is a semiconductor substrate of a first conductivity type,

the forming the diffusion layer comprises:

forming a front surface semiconductor region of the first conductivity type which is exposed on the front surface of the semiconductor substrate by an ion implantation of first conductivity type impurities to the semiconductor substrate from the front surface side of the semiconductor substrate;

forming a top body region of a second conductivity type at a position deeper than the front surface semiconductor region by an ion implantation of second conductivity type impurities to the semiconductor substrate from the front surface side of the semiconductor substrate; and

forming a barrier region of the first conductivity type at a position deeper than the top body region by an ion implantation of first conductivity type impurities to the semiconductor substrate from the front surface side of the semiconductor substrate, the barrier region having an increased first conductivity impurity density than before the ion implantation, and

the front surface semiconductor region, the top body region, and the barrier region are formed adjacent to a part of the gate insulating film which is formed on a side surface of the trench.

6. The manufacturing method as in claim 5, wherein

the forming the diffusion layer further comprises:

forming a bottom body region of the second conductivity type at a position deeper than the barrier region by an ion implantation of second conductivity type impurities to the semiconductor substrate from the front surface side of the semiconductor substrate,

wherein the bottom body region is formed adjacent to the part of the gate insulating film which is formed on the side surface of the trench.

7. A semiconductor device comprising:

a semiconductor substrate;

a trench provided in a front surface of the semiconductor substrate;

a gate insulating film covering an inner surface of the trench; and

a gate electrode provided on an inner side of the gate insulating film, wherein

a front surface of the gate electrode is provided at a position deeper than the front surface of the semiconductor substrate, and a front surface of a first part of the gate electrode, which is located at a center in a width direction of the trench, is provided at a position shallower than a front surface of a second part of the gate electrode which is in contact with the gate insulating film.

8. The semiconductor device as in claim 7, wherein

the front surface of the second part is provided at a depth within 400 nm from the front surface of the semiconductor substrate.

9. The semiconductor device as in claim 7, further comprising:

a front surface semiconductor region of a first conductivity type exposed on the front surface of the semiconductor substrate;

a top body region of a second conductivity type provided at a position deeper than the front surface semiconductor region;

a barrier region of the first conductivity type provided at a position deeper than the top body region; and

a drift region of the first conductivity type having a lower first conductivity type impurity density than the barrier region, and provided at a position deeper than the barrier region,

wherein the trench penetrates the front surface semiconductor region, the top body region, and the barrier region, and

a lower end of the trench projects into the drift region.

10. The semiconductor device as in claim 9, further comprising:

a bottom body region provided at a position deeper than the barrier region and shallower than the drift region,

wherein the trench further penetrates the bottom body region.