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METHOD FOR MANUFACTURING COA LIQUID CRYSTAL PANEL AND COA LIQUID CRYSTAL PANEL

  • US 20170038653A1
  • Filed: 04/03/2015
  • Published: 02/09/2017
  • Est. Priority Date: 03/18/2015
  • Status: Abandoned Application
First Claim
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1. A method for manufacturing a color filter on array (COA) liquid crystal panel, comprising the following steps:

  • (1) providing an array substrate and a glass substrate,wherein the array substrate comprises red, green, and blue sub pixel zones and each of the sub pixel zones comprises a base plate, an amorphous silicon layer formed on the base plate, a buffer layer formed on the amorphous silicon layer and the base plate, a poly-silicon layer formed on the buffer layer and corresponding to the amorphous silicon layer, a gate insulation layer formed on the poly-silicon layer and the buffer layer, a gate terminal formed on the gate insulation layer and corresponding to the poly-silicon layer, a scan line formed on the gate insulation layer, an interlayer insulation layer formed on the gate terminal, the scan line, and the gate insulation layer, source/drain terminals formed on the interlayer insulation layer, and a signal line formed on the interlayer insulation layer and arranged to perpendicularly intersect the scan line in a horizontal direction, andthe interlayer insulation layer and the gate insulation layer comprise first vias formed therethrough at locations above the poly-silicon layer and the source/drain terminals are respectively set in engagement with the poly-silicon layer through the first vias;

    (2) forming a passivation layer on the source/drain terminals, the signal line, and the interlayer insulation layer;

    (3) forming a color resist layer on the passivation layer,wherein the color resist layer comprises red, green, and blue color resist blocks respectively corresponding to the red, green, and blue sub pixel zone and two of the color resist blocks that are arranged to be adjacent to each other in a lateral direction form therebetween a first intersection zone, the first intersection zone being located above the signal line, and two of the color resist blocks that are arranged to be adjacent to each other in a longitudinal direction form therebetween a second intersection zone, the second intersection zone being located above the scan line;

    (4) forming a planarization layer on the color resist layer and forming a second via in the planarization layer, the color resist layer, and the passivation layer to be located above the source/drain terminals;

    (5) depositing and patterning a pixel electrode layer on the planarization layer and forming a common electrode layer on the glass substrate,wherein the pixel electrode layer is set in engagement with the source/drain terminals through the second via and the pixel electrode layer comprises a pixel electrode block corresponding to the sub pixel zones and the pixel electrode block has a lateral border located above the scan line and a longitudinal border located above the signal line; and

    (6) laminating the array substrate and the glass substrate with each other and filling therebetween a liquid crystal layer.

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