METHOD FOR MANUFACTURING COA LIQUID CRYSTAL PANEL AND COA LIQUID CRYSTAL PANEL

• US 20170038653A1
• Filed: 04/03/2015
• Published: 02/09/2017
• Est. Priority Date: 03/18/2015
• Status: Abandoned Application

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: XU, Hongyuan, SUN, Bo
• Application Number:
  US14/758,563
• Publication Number:
  US 20170038653A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/133302 Rigid substrates, e.g. inorganic substrates
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133357 Planarisation layers
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13685 Top gates
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2201/52 RGB geometrical arrangements
• CPC Class Codes: G02F 2202/02 organic material
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/04 : characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/78633 : with a light shield
• CPC Class Codes: H01L 29/78675 : with normal-type structure, e.g. with top gate

Abstract

The present invention provides a method for manufacturing a COA liquid crystal panel and a COA liquid crystal panel. The method includes forming a planarization layer on a color resist layer to eliminate height difference resulting from stacking or overlapping of adjacent color resist blocks and also includes forming a pixel electrode layer on the planarization layer to set a pixel electrode block thereof located above sub pixel zones in such a way that a lateral border thereof is located above a scan line and a longitudinal border thereof is located above a signal line, whereby the array substrate achieves self-shielding of leaking light in the lateral direction by means of the scan line and also achieve self-shielding of leaking light in the longitudinal direction by means of the signal line and thus no black matrix is necessary is shielding leaking light. As such, the manufacturing process is simplified, the aperture ratio is heightened, and a gate terminal and an amorphous silicon layer are respectively formed on upper and lower sides of the poly-silicon layer to shield light, preventing light leakage from occurring in the site of a channel to affect the liquid crystal layer and also to prevent light leakage caused by misalignment between an array substrate and a glass substrate or panel flexing of a curved display device.

Claims

1. A method for manufacturing a color filter on array (COA) liquid crystal panel, comprising the following steps:

(1) providing an array substrate and a glass substrate,

wherein the array substrate comprises red, green, and blue sub pixel zones and each of the sub pixel zones comprises a base plate, an amorphous silicon layer formed on the base plate, a buffer layer formed on the amorphous silicon layer and the base plate, a poly-silicon layer formed on the buffer layer and corresponding to the amorphous silicon layer, a gate insulation layer formed on the poly-silicon layer and the buffer layer, a gate terminal formed on the gate insulation layer and corresponding to the poly-silicon layer, a scan line formed on the gate insulation layer, an interlayer insulation layer formed on the gate terminal, the scan line, and the gate insulation layer, source/drain terminals formed on the interlayer insulation layer, and a signal line formed on the interlayer insulation layer and arranged to perpendicularly intersect the scan line in a horizontal direction, and

the interlayer insulation layer and the gate insulation layer comprise first vias formed therethrough at locations above the poly-silicon layer and the source/drain terminals are respectively set in engagement with the poly-silicon layer through the first vias;

(2) forming a passivation layer on the source/drain terminals, the signal line, and the interlayer insulation layer;

(3) forming a color resist layer on the passivation layer,

wherein the color resist layer comprises red, green, and blue color resist blocks respectively corresponding to the red, green, and blue sub pixel zone and two of the color resist blocks that are arranged to be adjacent to each other in a lateral direction form therebetween a first intersection zone, the first intersection zone being located above the signal line, and two of the color resist blocks that are arranged to be adjacent to each other in a longitudinal direction form therebetween a second intersection zone, the second intersection zone being located above the scan line;

(4) forming a planarization layer on the color resist layer and forming a second via in the planarization layer, the color resist layer, and the passivation layer to be located above the source/drain terminals;

(5) depositing and patterning a pixel electrode layer on the planarization layer and forming a common electrode layer on the glass substrate,

wherein the pixel electrode layer is set in engagement with the source/drain terminals through the second via and the pixel electrode layer comprises a pixel electrode block corresponding to the sub pixel zones and the pixel electrode block has a lateral border located above the scan line and a longitudinal border located above the signal line; and

(6) laminating the array substrate and the glass substrate with each other and filling therebetween a liquid crystal layer.

2. The method for manufacturing the COA liquid crystal panel as claimed in claim 1, wherein the poly-silicon layer comprises a channel, two N-type light doping areas respectively located on opposite sides of the channel, and two N-type heavy doping areas respectively located on outer sides of the two N-type light doping areas, the first vias being arranged above and corresponding to the N-type heavy doping areas, the source/drain terminals being respectively connected by the first vias with the N-type heavy doping areas.

3. The method for manufacturing the COA liquid crystal panel as claimed in claim 1, wherein step (2) uses chemical vapor deposition to form the passivation layer.

4. The method for manufacturing the COA liquid crystal panel as claimed in claim 1, wherein step (3) uses a coating process to form the color resist layer.

5. The method for manufacturing the COA liquid crystal panel as claimed in claim 1, wherein step (4) uses a coating process to form the planarization layer, the planarization layer being formed of a transparent organic material.

6. The method for manufacturing the COA liquid crystal panel as claimed in claim 1, wherein step (5) uses physical vapor deposition to form the pixel electrode layer, the pixel electrode layer and the common electrode layer being both formed of a material of indium tin oxide.

7. A color filter on array (COA) liquid crystal panel, comprising an array substrate, a glass substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the glass substrate;

wherein the array substrate comprises red, green, and blue sub pixel zones, each of the sub pixel zones comprising a base plate, an amorphous silicon layer formed on the base plate, a buffer layer formed on the amorphous silicon layer and the base plate, a poly-silicon layer formed on the buffer layer and corresponding to the amorphous silicon layer, a gate insulation layer formed on the poly-silicon layer and the buffer layer, a gate terminal formed on the gate insulation layer and corresponding to the poly-silicon layer, a scan line formed on the gate insulation layer, an interlayer insulation layer formed on the gate terminal, the scan line, and the gate insulation layer, source/drain terminals formed on the interlayer insulation layer, a signal line formed on the interlayer insulation layer and arranged to perpendicularly intersect the scan line in a horizontal direction, a passivation layer formed on the source/drain terminals, the signal line, and the interlayer insulation layer, a color resist layer formed on the passivation layer, a planarization layer formed on the color resist layer, and a pixel electrode layer formed on the planarization layer;

the interlayer insulation layer and the gate insulation layer comprise first vias formed therethrough at locations above the poly-silicon layer, the planarization layer, the color resist layer, and the passivation layer comprising a second via formed therethrough at a location above the source/drain terminals, the source/drain terminals being respectively set in engagement with the poly-silicon layer through the first vias, the pixel electrode layer being set in engagement with the source/drain terminals through the second via; and

the color resist layer comprises red, green, and blue color resist blocks respectively corresponding to the red, green, and blue sub pixel zones, two of the color resist blocks that are arranged to be adjacent to each other in a lateral direction forming therebetween a first intersection zone, the first intersection zone being located above the signal line, two of the color resist blocks that are arranged to be adjacent to each other in a longitudinal direction forming therebetween a second intersection zone, the second intersection zone being located above the scan line, the pixel electrode layer comprising a pixel electrode block corresponding to the sub pixel zones, the pixel electrode block having a lateral border located above the scan line and a longitudinal border located above the signal line.

8. The COA liquid crystal panel as claimed in claim 7, wherein the poly-silicon layer comprises a channel, two N-type light doping areas respectively located on opposite sides of the channel, and two N-type heavy doping areas respectively located on outer sides of the two N-type light doping areas, the first vias being arranged above and corresponding to the N-type heavy doping areas, the source/drain terminals being respectively connected by the first vias with the N-type heavy doping areas.

9. The COA liquid crystal panel as claimed in claim 7, wherein the planarization layer is formed of a transparent organic material.

10. The COA liquid crystal panel as claimed in claim 7, wherein the glass substrate comprises a common electrode layer formed thereon and the pixel electrode layer and the common electrode layer are both formed of a material of indium tin oxide.

11. A color filter on array (COA) liquid crystal panel, comprising an array substrate, a glass substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the glass substrate;

wherein the array substrate comprises red, green, and blue sub pixel zones, each of the sub pixel zones comprising a base plate, an amorphous silicon layer formed on the base plate, a buffer layer formed on the amorphous silicon layer and the base plate, a poly-silicon layer formed on the buffer layer and corresponding to the amorphous silicon layer, a gate insulation layer formed on the poly-silicon layer and the buffer layer, a gate terminal formed on the gate insulation layer and corresponding to the poly-silicon layer, a scan line formed on the gate insulation layer, an interlayer insulation layer formed on the gate terminal, the scan line, and the gate insulation layer, source/drain terminals formed on the interlayer insulation layer, a signal line formed on the interlayer insulation layer and arranged to perpendicularly intersect the scan line in a horizontal direction, a passivation layer formed on the source/drain terminals, the signal line, and the interlayer insulation layer, a color resist layer formed on the passivation layer, a planarization layer formed on the color resist layer, and a pixel electrode layer formed on the planarization layer;

the interlayer insulation layer and the gate insulation layer comprise first vias formed therethrough at locations above the poly-silicon layer, the planarization layer, the color resist layer, and the passivation layer comprising a second via formed therethrough at a location above the source/drain terminals, the source/drain terminals being respectively set in engagement with the poly-silicon layer through the first vias, the pixel electrode layer being set in engagement with the source/drain terminals through the second via;

the color resist layer comprises red, green, and blue color resist blocks respectively corresponding to the red, green, and blue sub pixel zones, two of the color resist blocks that are arranged to be adjacent to each other in a lateral direction forming therebetween a first intersection zone, the first intersection zone being located above the signal line, two of the color resist blocks that are arranged to be adjacent to each other in a longitudinal direction forming therebetween a second intersection zone, the second intersection zone being located above the scan line, the pixel electrode layer comprising a pixel electrode block corresponding to the sub pixel zones, the pixel electrode block having a lateral border located above the scan line and a longitudinal border located above the signal line;

wherein the poly-silicon layer comprises a channel, two N-type light doping areas respectively located on opposite sides of the channel, and two N-type heavy doping areas respectively located on outer sides of the two N-type light doping areas, the first vias being arranged above and corresponding to the N-type heavy doping areas, the source/drain terminals being respectively connected by the first vias with the N-type heavy doping areas; and

wherein the planarization layer is formed of a transparent organic material.

12. The COA liquid crystal panel as claimed in claim 11, wherein the glass substrate comprises a common electrode layer formed thereon and the pixel electrode layer and the common electrode layer are both formed of a material of indium tin oxide.