POWER DISTRIBUTION NETWORK (PDN) DROOP/OVERSHOOT MITIGATION

• US 20170038814A1
• Filed: 08/03/2015
• Published: 02/09/2017
• Est. Priority Date: 08/03/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Pal, Dipti Ranjan
• Granted Patent: US 9,798,376 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In one embodiment, a method for activating one or more processors comprises reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors. The method also comprises activating the one or more processors after the frequency of the clock signal is reduced, and increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.

Claims

1. A processing system, comprising:

a plurality of processors;

a clock device configured to generate an input clock signal;

a frequency adjuster configured to receive the input clock signal from the clock device, and to output an output clock signal to the plurality of processors based on the input clock signal; and

a power manager configured to receive a signal to active one or more of the processors, wherein, in response to the signal, the power manager is configured to instruct the frequency adjuster to reduce a frequency of the output clock signal from a first clock frequency to a second clock frequency, to active the one or more of the processors while the frequency of the output clock signal is at the second clock frequency, and to instruct the frequency adjuster to increase the frequency of the output clock signal from the second clock frequency to the first clock frequency after the one or more of the processors are activated.

2. The processing system of claim 1, wherein the first clock frequency is approximately equal to a frequency of the input clock signal.

3. The processing system of claim 2, wherein the second clock frequency is approximately equal to 20% to 80% of the first clock frequency.

4. The processing system of claim 1, wherein one or more other ones of the processors are in an active mode while the power manager actives the one or more of the processors.

5. The processing system of claim 1, wherein the power manager actives the one or more of the processors by un-gating internal clock paths in the one or more of the processors.

6. The processing system of claim 1, wherein the frequency adjuster is configured to reduce the frequency of the output clock signal by selectively swallowing pulses of the input clock signal.

7. The processing system of claim 1, wherein the frequency adjuster is configured to reduce the frequency of the output clock signal by dividing a frequency of the input clock signal.

8. The processing system of claim 1, wherein the signal to active the one or more of the processors comprises an interrupt signal.

9. The processing system of claim 8, wherein the power manager is configured to place the one or more of the processors in an idle mode in response to execution of a wait-for-interrupt (WFI) instruction, and the interrupt signal is received after the one or more of the processors are placed in the idle mode.

10. The processing system of claim 1, wherein the power manager is configured to determine the second clock frequency based on the one or more of the processors to be activated in response to the signal, and one or more other ones of the processors that are in an active state at a time the signal is received.

11. The processing system of claim 10, wherein the power manager is further configured to determine the second clock frequency based on the first clock frequency.

12. A method for activating one or more processors, comprising:

reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors;

activating the one or more processors after the frequency of the clock signal is reduced; and

increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.

13. The method of claim 12, wherein the second clock frequency is approximately equal to 20% to 80% of the first clock frequency.

14. The method of claim 12, wherein one or more other ones of the plurality of processors are in an active mode while the one or more processors are activated.

15. The method of claim 12, wherein activating the one or more processors comprises un-gating internal clock paths in the one or more processors.

16. The method of claim 12, further comprising:

placing the one or more processors in an idle mode in response to execution of a wait-for-interrupt (WFI) instruction; and

receiving an interrupt signal after the one or more processors are placed in the idle mode;

wherein the one or more processors are activated in response to the interrupt signal.

17. The method of claim 12, further comprising determining the second clock frequency based on the one or more processors, and one or more other ones of the plurality of processors that are already in an active state at a time the determination is made.

18. The method of claim 17, wherein determining the second clock frequency further comprises determining the second clock frequency based on the first clock frequency.

19. An apparatus for activating one or more processors, comprising:

means for reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors;

means for activating the one or more processors after the frequency of the clock signal is reduced; and

means for increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.

20. The apparatus of claim 19, wherein the second clock frequency is approximately equal to 20% to 80% of the first clock frequency.

21. The apparatus of claim 19, wherein one or more other ones of the plurality of processors are in an active mode while the one or more processors are activated.

22. The apparatus of claim 19, wherein the means for activating the one or more processors comprises means for un-gating internal clock paths in the one or more processors.

23. The apparatus of claim 19, further comprising:

means for placing the one or more processors in an idle mode in response to execution of a wait-for-interrupt (WFI) instruction; and

means for receiving an interrupt signal after the one or more processors are placed in the idle mode;

wherein the means for activating the one or more processors activates the one or more processors in response to the interrupt signal.

24. The apparatus of claim 19, further comprising means for determining the second clock frequency based on the one or more processors, and one or more other ones of the plurality of processors that are already in an active state at a time the determination is made.

25. The apparatus of claim 24, wherein the means for determining the second clock frequency further determines the second clock frequency based on the first clock frequency.