DISPLAY DRIVER INTEGRATED CIRCUIT AND ELECTRONIC APPARATUS INCLUDING THE SAME

• US 20170038894A1
• Filed: 05/20/2016
• Published: 02/09/2017
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JEONG, Eui-hyuk, KIM, Si-woo, KIM, Jeong-pyo
• Granted Patent: US 10,067,595 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G09G 2330/028 Generation of voltages supplied to electrode drivers in a matrix display other than LCD
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A display driver integrated circuit (IC) and an electronic apparatus including the same are provided. The display driver IC includes a booster configured to boost an external power supply voltage applied to a first node to a same level as that of an internal power supply voltage, and a power supplier including a power level adjustor configured to activate a current path between a second node and ground in response to a control signal indicating entry into a first mode and form a current path between the first node and the second node when the internal power supply voltage at the second node is equal to a reference voltage.

Claims

1. A display driver integrated circuit (IC) comprising:

a booster configured to boost an external power supply voltage applied to a first node to a voltage level of an internal power supply voltage applied to a second node; and

a power level adjustor configured to,

form a current path between the second node and ground, if the display driver IC enters a first mode, and

form a current path between the first node and the second node, if the internal power supply voltage at the second node is equal to a reference voltage.

2. The display driver IC of claim 1, wherein the power level adjustor comprises:

a first current path configured to electrically connect the second node to the ground, if a control signal indicates that the display driver IC has entered the first mode;

an internal power level detector configured to detect the internal power supply voltage at the second node, and selectively output an enable signal based on the detected internal power supply voltage and the reference voltage; and

a second current path configured to electrically connect the first node to the second node, if the internal power level detector outputs the enable signal.

3. The display driver IC of claim 2, wherein the external power supply voltage is a positive power supply voltage, and the internal power supply voltage is a gate high voltage.

4. The display driver IC of claim 3, wherein the power level adjustor comprises:

a first PMOS transistor having a source, a drain and a gate, the source of the first PMOS transistor connected to the second node and the gate of the first PMOS transistor configured to receive the control signal;

a second PMOS transistor having a source, a drain and a gate, the source of the second PMOS transistor connected to the drain of the first PMOS transistor, the drain of the second PMOS transistor connected to the ground, and the gate of the second PMOS transistor configured to receive a first voltage;

first current source connected to the second node, the first current source configured to supply a current having a first current level;

a third PMOS transistor connected between the first current source and a third node, the third PMOS transistor having a gate configured to receive the first voltage;

a second current source connected between the third node and the ground, the second current source configured to supply a current having a second current level, the second current level being less than the first current level; and

a fourth PMOS transistor connected between the first node and the second node, the fourth PMOS transistor having a gate configured to receive the enable signal from the third node.

5. The display driver IC of claim 4, wherein the first voltage is the positive power supply voltage, and the reference voltage is greater than the positive power supply voltage by a threshold voltage of the third PMOS transistor.

6. The display driver IC of claim 2, wherein the external power supply voltage is a negative power supply voltage, and the internal power supply voltage is a gate low voltage.

7. The display driver IC of claim 6, wherein the power level adjustor comprises:

a first NMOS transistor having a source, a drain and a gate, the drain of the first NMOS connected to the second node and the gate of the first NMOS transistor configured to receive the control signal;

a second NMOS transistor having a source, a drain and a gate, the drain of the second NMOS transistor connected to the source of the first NMOS transistor, the source of the second NMOS transistor connected to the ground, and the gate of the second NMOS transistor configured to receive a second voltage;

a first current source connected to the second node, the first current source configured to supply a current having a first current level;

a third NMOS transistor connected between the first current source and a third node, a gate of the third NMOS transistor configured to receive the second voltage;

a second current source connected between the third NMOS transistor and the ground, the second current source configured to supply a current having a second current level, the second current level being greater than the first current level; and

a fourth NMOS transistor connected between the first node and the second node, the fourth NMOS transistor having a gate configured to receive the enable signal from the third node.

8. The display driver IC of claim 7, wherein the second voltage is the negative power supply voltage, and the reference voltage is greater than the negative power supply voltage by a threshold voltage of the third NMOS transistor.

9. The display driver IC of claim 1, wherein the first mode is an operation mode other than a normal mode for image data processing.

10. An electronic apparatus comprising:

an in-cell type touch panel including at least one display pixel and at least one touch pixel;

a power management IC (PMIC) configured to generate an external power supply voltage, and to apply the external power supply voltage to a first node; and

a display driver integrated circuit (IC) configured to drive the in-cell type touch panel, the display driver IC including a power supplier configured to,

activate a first current path connecting the first node to ground when the display driver IC enters a first mode, and

activate a second current path connecting the first node to a second node after activating the first current path, the second node having an internal power supply voltage applied thereto.

11. The electronic apparatus of claim 10, wherein the power supplier comprises:

a first power supplier configured to,

receive a positive power supply voltage as the external power supply voltage from the PMIC, and

driving gate lines of the in-cell type touch panel by performing boosting, discharging, and pre-charging between the positive power supply voltage and a gate high voltage; and

a second power supplier configured to,

receive a negative power supply voltage as the external power supply voltage from the PMIC, and

driving the gate lines of the in-cell type touch panel by performing boosting, discharging, and pre-charging between the negative power supply voltage and a gate low voltage.

12. The electronic apparatus of claim 11, wherein the first power supplier comprises:

a first PMOS transistor having a source, a drain and a gate, the source of the first PMOS connected to the second node and the gate of the first PMOS transistor configured to receive a control signal indicating that the display driver IC has entered the first mode;

a second PMOS transistor having a source, a drain and a gate, the source of the second PMOS transistor connected to the drain of the first PMOS transistor, the drain of the second PMOS transistor connected to the ground, and the gate of the second PMOS transistor configured to receive a first voltage;

a first current source connected to the second node, the first current source configured to supply a current having a first current level;

a third PMOS transistor connected between the first current source and a third node, the third PMOS transistor having a gate configured to receive the first voltage;

a second current source connected between the third node and the ground, the second current source configured to supply a current having a second current level, the second current level being less than the first current level; and

a fourth PMOS transistor connected between the first node and the second node, the fourth PMOS transistor having a gate configured to receive the enable signal from the third node.

13. The electronic apparatus of claim 11, wherein the second power supplier comprises:

a first NMOS transistor having a source, a drain and a gate, the drain of the first NMOS connected to the second node and the gate of the first NMOS transistor configured to receive a control signal indicating that the display driver IC has entered the first mode;

a second NMOS transistor having a source, a drain and a gate, the drain of the second NMOS transistor connected to the source of the first NMOS transistor, the source of the second NMOS transistor connected to the ground, and the gate of the second NMOS transistor configured to receive a second voltage;

a first current source connected to the second node and a third node, the first current source configured to supply a current having a first current level;

a third NMOS transistor connected between the first current source and the third node, a gate of the third NMOS transistor configured to receive the second voltage;

a second current source connected between the third NMOS transistor and the ground, the second current source configured to supply a current having a second current level, the second current level being greater than the first current level; and

a fourth NMOS transistor connected between the first node and the second node, the fourth NMOS transistor having a gate configured to receive the enable signal from the third node.

14. The electronic apparatus of claim 10, wherein the in-cell type touch panel comprises:

a gate driver configured to control activation of gate lines of the in-cell type touch panel via the internal power supply voltage.

15. The electronic apparatus of claim 10, wherein the display driver IC is further configured to transmit a scan signal to the in-cell type touch panel to sense a touch position on the in-cell type touch panel.

16. A display driver integrated circuit (IC) comprising:

a booster configured to selectively boost an external voltage applied to a first node to an internal voltage applied to a second node; and

a power level adjusting circuit configured to,

connect the second node to ground via a first current path to decrease the internal voltage, if the display driver IC enters a low power mode,

deactivate the first current path to ground, if the internal voltage reaches a reference voltage, and

connect the first node to the second node via a second current path after deactivating the first current path such that the external voltage discharges to a level of the internal voltage.

17. The display driver IC of claim 16, wherein, if the display driver IC enters the low power mode, the power level adjusting circuit is configured to bypass the booster by connecting the first node to the second node via the second current path after deactivating the first current path.

18. The display driver IC of claim 16, wherein the power level adjusting circuit comprises:

a detector configured to,

detect the internal voltage at the second node, and

activate the second current path based on the internal voltage and the reference voltage.

19. The display driver IC of claim 16, wherein the reference voltage is one of greater than the external voltage by a threshold voltage of a transistor within one of the first current path and the second current path and less than the external voltage by the threshold voltage of the transistor.

20. The display driver IC of claim 16, wherein the display driver IC is configured to,

receive the external voltage from an output terminal of a power management IC (PMIC) connected to the first node,

drive gate lines of a touch panel via the internal voltage, and

prevent a momentary increase in a potential of the output terminal when the first node is connected to the second node by discharging the internal voltage to a same level as the external voltage in two-stages, if the display driver IC enters the low power mode.