Apparatus and Method to Provide Cache Move with Non-Volatile Mass Memory System

• US 20170038975A1
• Filed: 08/12/2016
• Published: 02/09/2017
• Est. Priority Date: 01/26/2012
• Status: Active Grant

• Current Assignee: Memory Technologies LLC (Pendrell Corporation)
• Original Assignee: Memory Technologies LLC (Pendrell Corporation)
• Inventors: Mylly, Kimmo J., Klint, Jani J., Hyvonen, Jani, Hill, Tapio, Vihmalo, Jukka-Pekka, Floman, Matti K.
• Granted Patent: US 10,877,665 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method includes, in one non-limiting embodiment, receiving a command originating from an initiator at a controller associated with a non-volatile mass memory coupled with a host device, the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory; moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory; and acknowledging to the initiator that the command to write the data to the non-volatile mass memory has been executed. An apparatus configured to perform the method is also described.

Claims

1-20. -20. (canceled)

21. A memory module comprising:

a control module;

a memory that is readable and writable by the control module; and

an interface for connecting the memory module to a memory controller of a host device;

the control module configured to;

receive, from the memory controller of the host device, a command associated with data stored in the memory; and

perform, based at least in part on the command, one or more elementary memory operations within the memory module, wherein the one or more elementary memory operations include a data move operation and a data fill operation.

22. The memory module of claim 21, the control module further configured to perform the one or more elementary memory operations in the memory module autonomously following receipt of the command.

23. The memory module of claim 21, the data fill operation including setting a specified plurality of memory locations in the memory to a specified value.

24. The memory module of claim 23, the control module further configured to determine a fill pattern to set the specified plurality of memory locations in the memory to the specified value, wherein the fill pattern is one of a predetermined fill pattern stored in the memory module or a received fill pattern included in the command from the memory controller of the host device.

25. The memory module of claim 21, the data move operation including copying the data from a first specified plurality of memory locations in the memory to a second specified plurality of memory locations.

26. The memory module of claim 25, wherein the data move operation further includes setting the first specified plurality of memory locations in the memory to at least one of a predetermined value stored in the memory module or one or more values included in the command.

27. The memory module of claim 21, wherein the memory module is one of a dynamic random access memory (DRAM) module or a mass memory module.

28. A method comprising:

receiving, from a memory controller of a host device, a command associated with data stored in a memory; and

performing, based at least in part on the command, one or more elementary memory operations within a memory module associated with the memory, wherein the one or more elementary memory operations include a data move operation and a data fill operation.

29. The method of claim 28, further comprising performing the one or more elementary memory operations in the memory module autonomously following receipt of the command.

30. The method of claim 28, the data fill operation including setting a specified plurality of memory locations in the memory to a specified value.

31. The method of claim 30, further comprising determining a fill pattern to set the specified plurality of memory locations in the memory to the specified value, wherein the fill pattern is one of a predetermined fill pattern stored in the memory module or a received fill pattern received in the command from the memory controller of the host device.

32. The method of claim 28, the data move operation including copying the data from a first specified plurality of memory locations in the memory to a second specified plurality of memory locations.

33. The method of claim 32, the data move operation further including setting the first specified plurality of memory locations in the memory to a predetermined value.

34. A host apparatus comprising:

a memory controller; and

an interface for connecting the memory controller to a memory module;

the memory controller configured to;

transmit, to the memory module, a command associated with data stored in a memory of the memory module thereby causing the memory module to perform one or more elementary memory operations within the memory module, wherein the one or more elementary memory operations include a data move operation and a configurable data fill operation, and

wherein the memory controller is controlled by one of a mass memory module or a mass memory host controller.

35. The host apparatus of claim 34, further comprising the mass memory host controller, wherein the command is initiated by the mass memory host controller and transmitted to the memory module by the memory controller via the interface.

36. The host apparatus of claim 34, wherein the one or more elementary memory operations comprise the configurable data fill operation, the configurable data fill operation including setting a specified plurality of memory locations in the memory to a specified value.

37. The host apparatus of claim 36, the memory controller further configured to transmit a fill pattern to the memory module to set the specified plurality of memory locations in the memory to the specified value.

38. The host apparatus of claim 34, wherein the one or more elementary memory operations comprise the data move operation, the data move operation including copying the data from a first specified plurality of memory locations in the memory to a second specified plurality of memory locations.

39. The host apparatus of claim 38, wherein the data move operation further includes setting the first specified plurality of memory locations in the memory to a predetermined value.

40. The host apparatus of claim 34, wherein the memory module is a dynamic random access memory (DRAM) module.

41. A dynamic random access memory (DRAM) memory module comprising:

a control module;

a memory that is readable and writable by the control module; and

an interface for connecting the DRAM memory module to a memory controller of a host device;

the control module configured to;

receive, from the memory controller of the host device, one or more commands associated with a plurality of memory locations in the memory;

determine a fill pattern to set the plurality of memory locations in the memory to a specified value, wherein the fill pattern is one of a predetermined fill pattern stored in the DRAM memory module or a received fill pattern included in the one or more commands from the memory controller of the host device; and

perform, based at least in part on the one or more commands, a data fill operation, wherein the data fill operation includes setting the plurality of memory locations in the memory to the specified value.

42. The DRAM memory module of claim 41, wherein the specified value is at least one of a single zero bit, a single one bit, a first pattern of two bits, a second pattern of four bits, or a third pattern of a plurality of bits.