SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20170040246A1
• Filed: 05/23/2016
• Published: 02/09/2017
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SHUTO, Takao, ISHIHARA, Kaoru
• Granted Patent: US 9,984,959 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

An object of the present invention is to improve the performance of a semiconductor device that transmits signals using inductive coupling of inductors.

A semiconductor device includes a first semiconductor chip having a first inductor formed on the first top surface side and a second semiconductor chip having a second inductor formed on the second top surface side. The first semiconductor chip and the second semiconductor chip are laminated on each other so that the first top surface and the second top surface face each other. Further, a plurality of first pads of the first semiconductor chip is provided along each of a first chip side and a second chip side among four sides of the first top surface. Further, each of the first pads of the first semiconductor chip is not overlapped with the second semiconductor chip in planar view.

Claims

1. A semiconductor device comprising:

a first semiconductor chip including a first top surface in a quadrangular shape, a first back surface opposite to the first top surface, a plurality of first pads arranged over the first top surface, and a first inductor that is provided on the first top surface side and is electrically coupled to the first pads;

a second semiconductor chip including a second top surface in a quadrangular shape, a second back surface opposite to the second top surface, a plurality of second pads arranged over the second top surface, and a second inductor that is provided on the second top surface side and is electrically coupled to the second pads, the second inductor being mounted over the first semiconductor chip through a first insulating film so as to face the first inductor;

a chip mounting part over which the first semiconductor chip and the second semiconductor chip are mounted;

a plurality of leads mounted around the chip mounting part;

a plurality of first wires through which each of a plurality of first leads of the leads and each of the first pads of the first semiconductor chip are electrically coupled to each other; and

a plurality of second wires through which each of a plurality of second leads of the leads and each of the second pads of the second semiconductor chip are electrically coupled to each other,

wherein the first pads are provided along each of a first chip side and a second chip side intersecting with the first chip side among four sides of the first top surface, and

wherein the second semiconductor chip is mounted over the first semiconductor chip in such a manner that each of the first pads of the first semiconductor chip is not overlapped with the second semiconductor chip in first planar view viewed from the first top surface side of the first semiconductor chip and each of the second pads of the second semiconductor chip is not overlapped with the first semiconductor chip in second planar view viewed from the second top surface side of the second semiconductor chip.

2. The semiconductor device according to claim 1,

wherein the second semiconductor chip is mounted over the first semiconductor chip in such a manner that each of the second pads is not overlapped with the chip mounting part in the second planar view.

3. The semiconductor device according to claim 1,

wherein a plurality of hanging leads coupled to the chip mounting part is further provided,

wherein the chip mounting part has a first base material side, a second base material side extending in the direction intersecting with the first base material side, a third base material side facing the first base material side, a fourth base material side that faces the second base material side and extends in the direction intersecting with the third base material side, a first corner part formed by the third base material side and the fourth base material side, and a second corner part formed by the first base material side and the second base material side,

wherein the second semiconductor chip is mounted over the first semiconductor chip so as to be overlapped with the first corner part in the first planar view, and

wherein the hanging leads are coupled to parts other than the first corner part and the second corner part of the chip mounting part.

4. The semiconductor device according to claim 1,

wherein the area of a part where a projected part of the second semiconductor chip not overlapped with the first semiconductor chip is overlapped with the chip mounting part is smaller than that of a part where the projected part is not overlapped with the chip mounting part.

5. The semiconductor device according to claim 1,

wherein the first semiconductor chip has the first chip side, the second chip side intersecting with the first chip side, a third chip side facing the first chip side, and a fourth chip side facing the third chip side,

wherein the second semiconductor chip has a fifth chip side arranged so as to be aligned along the first chip side of the first semiconductor chip, a sixth chip side intersecting with the fifth chip side, a seventh chip side facing the fifth chip side, and an eighth chip side facing the sixth chip side,

wherein the chip mounting part has a first base material side arranged so as to be aligned along the first chip side of the first semiconductor chip, a second base material side intersecting with the first base material side, a third base material side facing the first base material side, and a fourth base material side facing the second base material side, and

wherein a first distance from the third chip side of the first semiconductor chip to the third base material side of the chip mounting part is smaller than a second distance from the seventh chip side of the second semiconductor chip to the third base material side of the chip mounting part in the first planar view.

6. The semiconductor device according to claim 5,

wherein a third distance from the fourth chip side of the first semiconductor chip to the fourth base material side of the chip mounting part is smaller than a fourth distance from the eighth chip side of the second semiconductor chip to the fourth base material side of the chip mounting part in the first planar view.

7. The semiconductor device according to claim 6,

wherein third wires are coupled between the first base material side of the chip mounting part and the first chip side of the first semiconductor chip, and

wherein a fifth distance from the first base material side of the chip mounting part to the first chip side of the first semiconductor chip is larger than the first distance.

8. The semiconductor device according to claim 1,

wherein the area of a part where the first semiconductor chip is overlapped with the second semiconductor chip is larger than that of a part where the first semiconductor chip is not overlapped with the second semiconductor chip in the first planar view.

9. The semiconductor device according to claim 1,

wherein a metal film is formed over the second back surface of the second semiconductor chip, and

wherein third leads of the leads are electrically coupled to the metal film of the second back surface through the third wires.

10. The semiconductor device according to claim 9,

wherein the first semiconductor chip and the chip mounting part are electrically coupled to each other through fourth wires coupled to a part of the chip mounting part.

11. The semiconductor device according to claim 1,

wherein the chip mounting part has a first base material side, a second base material side extending in the direction intersecting with the first base material side, a third base material side facing the first base material side, a fourth base material side that faces the second base material side and extends in the direction intersecting with the third base material side, a first corner part formed by the third base material side and the fourth base material side, and a second corner part formed by the first base material side and the second base material side, and

wherein the second semiconductor chip is mounted over the first semiconductor chip so as to be overlapped with the first corner part and so as not to be overlapped with the second corner part in the first planar view.

12. The semiconductor device according to claim 11,

wherein the first semiconductor chip and the second semiconductor chip are sealed with a sealing body, and

wherein the sealing body has four sides and the leads protrude from the respective four sides in planar view.

13. The semiconductor device according to claim 1,

wherein the first insulating film is a film-like organic insulating film.

14. A manufacturing method of a semiconductor device comprising steps of:

(a) preparing a chip mounting part and a lead frame having the leads arranged around the chip mounting part;

(b) mounting over the chip mounting part a first semiconductor chip including a first top surface in a quadrangular shape, a first back surface opposite to the first top surface, the first pads arranged over the first top surface, and a first inductor that is provided on the first top surface side and is electrically coupled to the first pads;

(c) mounting over the first semiconductor chip through a first insulating film a second semiconductor chip including a second top surface in a quadrangular shape, a second back surface opposite to the second top surface, the second pads arranged over the second top surface, and a second inductor that is provided on the second top surface side and is electrically coupled to the second pads, the second inductor facing the first inductor; and

(d) electrically coupling each of the first leads of the leads to each of the first pads of the first semiconductor chip through a plurality of first wires and electrically coupling each of the second leads of the leads to each of the second pads of the second semiconductor chip through a plurality of second wires,

wherein the first pads are provided along each of a first chip side and a second chip side intersecting with the first chip side among four sides of the first top surface, and

wherein the second semiconductor chip is mounted over the first semiconductor chip in the step (c) in such a manner that each of the first pads of the first semiconductor chip is not overlapped with the second semiconductor chip in first planar view viewed from the first top surface side of the first semiconductor chip and each of the second pads of the second semiconductor chip is not overlapped with the first semiconductor chip in second planar view viewed from the second top surface side of the second semiconductor chip.

15. The manufacturing method of a semiconductor device according to claim 14,

wherein the second semiconductor chip is mounted over the first semiconductor chip in the step (c) in such a manner that each of the second pads is not overlapped with the chip mounting part.