SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20170040318A1
• Filed: 09/02/2015
• Published: 02/09/2017
• Est. Priority Date: 08/03/2015
• Status: Abandoned Application

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hung, Yu-Hsiang, Hsu, Chih-Kai, Lin, Chao-Hung, Fu, Ssu-I, Jenq, Jyh-Shyang
• Application Number:
  US14/842,855
• Publication Number:
  US 20170040318A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/45 Ohmic electrodes

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region; forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ILD) layer around the first gate structures and the second gate structures; forming a first patterned mask on the ILD layer; forming a second patterned mask on the second region; using the first patterned mask and the second patterned mask to remove all of the ILD layer from the first region and part of the ILD layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region;

forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ILD) layer around the first gate structures and the second gate structures;

forming a first patterned mask on the ILD layer and between the first region and the second region;

forming a second patterned mask on the second region; and

using the first patterned mask and the second patterned mask to remove all of the ILD layer from the first region and part of the ILD layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region.

2. The method of claim 1, further comprising forming a cap layer on the first gate structures, the second gate structures, and the ILD layer before forming the first patterned mask.

3. The method of claim 2, further comprising using the first patterned mask and the second patterned mask to remove part of the cap layer before removing all of the ILD layer from the first region and part of the ILD layer from the second region.

4. The method of claim 1, wherein the first patterned mask comprises TiN.

5. The method of claim 1, wherein a third gate structure on an edge of the first fin-shaped structure, the method further comprises using a third patterned mask to remove part of the third gate structure.

6. The method of claim 5, further comprising forming:

forming a metal layer in the first contact holes and the second contact holes and on the first patterned mask and the ILD layer; and

removing part of the metal layer and the first patterned mask for forming a plurality of first contact plugs in the first region and a plurality of second contact plugs in the second region.

7. A semiconductor device, comprising:

a substrate having a first region and a second region;

a first fin-shaped structure on the substrate and a second fin-shaped structure on the second region;

a plurality of first gate structures on the first fin-shaped structure, wherein the first gate structures comprise no interlayer dielectric (ILD) layer therebetween; and

a plurality of second gate structures on the second fin-shaped structure, wherein the second gate structures comprise a ILD layer therebetween.

8. The semiconductor device of claim 7, further comprising a spacer adjacent to each of the first gate structure and a plurality of first contact plugs between the first gate structures and contacting the spacer directly.

9. The semiconductor device of claim 7, further comprising a plurality of second contact plugs adjacent to the second gate structures, wherein the second contact plugs contact the ILD layer directly.

10. A semiconductor device, comprising:

a substrate having a fin-shaped structure thereon;

a plurality of first gate structures on the fin-shaped structure and an interlayer dielectric (ILD) layer around the first gate structures;

a first contact plug in the ILD layer adjacent to the first gate structures;

a first dielectric layer on the ILD layer;

a second contact plug in the first dielectric layer and contacting the first contact plug;

a second dielectric layer on the first dielectric layer;

a third contact plug in the second dielectric layer and contacting the second contact plug; and

a fourth contact plug in the second dielectric layer and the first dielectric layer and electrically connected to one of the first gate structures.

11. The semiconductor device of claim 10, further comprising:

a first stop layer between the ILD layer and the first dielectric layer; and

a second stop layer between the first dielectric layer and the second dielectric layer.

12. The semiconductor device of claim 10, wherein the second contact plug and the third contact plug are directly on top of the first contact plug.

13. The semiconductor device of claim 10, wherein each of the first contact plug, the second contact plug, the third contact plug, and the fourth contact plug comprises a U-shaped barrier layer.

14. The semiconductor device of claim 10, further comprising a second gate structure on an edge of the fin-shaped structure and a shallow trench isolation (STI).