Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle

• US 20170040326A1
• Filed: 10/11/2016
• Published: 02/09/2017
• Est. Priority Date: 08/05/2008
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Granted Patent: US 9,761,589 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

Claims

1-21. -21. (canceled)

22. A semiconductor memory cell comprising:

a transistor comprising a source region, a first floating body region, a drain region, and a gate; and

a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region, wherein;

a state of said memory cell is stored in said first floating body region,

said first floating body region and said second floating body region are common,

said silicon controlled rectifier device maintains a state of said memory cell, and

said transistor is usable to access said memory cell.

23. The semiconductor memory cell of claim 22, wherein:

said first floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type,

said cathode region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type,

said buried layer region has said second conductivity type; and

said anode region has said first conductivity type.

24. The semiconductor memory cell of claim 22, wherein said silicon controlled rectifier device maintains a state of said memory cell through a bias applied to said anode region.

25. The semiconductor memory cell of claim 24, wherein said bias applied to said anode region is a constant positive voltage bias.

26. The semiconductor memory cell of claim 24, wherein said bias applied to said anode region is a periodic pulse of positive voltage.

27. The semiconductor memory cell of claim 24, wherein said bias applied to said anode region results in at least two stable states.

28. The semiconductor memory cell of claim 22, wherein said transistor is formed in a fin structure.

29. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a transistor comprising a source region, a first floating body region, a drain region, and a gate; and

a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region, wherein;

a state of said memory cell is stored in said first floating body region,

said first floating body region and said second floating body region are common,

said silicon controlled rectifier device maintains a state of said memory cell,

said transistor is usable to access said memory cell, and wherein said anode region is commonly connected to at least two of said memory cells.

30. The semiconductor memory array of claim 29, wherein:

said first floating body region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type,

said cathode region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type,

said buried layer region has said second conductivity type; and

said anode region has said first conductivity type.

31. The semiconductor memory array of claim 29, wherein said silicon controlled rectifier device maintains a state of said memory cell through a bias applied to said anode region.

32. The semiconductor memory array of claim 31, wherein said bias applied to said anode region is a constant positive voltage bias.

33. The semiconductor memory array of claim 31, wherein said bias applied to said anode region is a periodic pulse of positive voltage.

34. The semiconductor memory array of claim 31, wherein said bias applied to said anode region results in at least two stable states.

35. The semiconductor memory array of claim 30, wherein said transistor is formed in a fin structure.

36. An integrated circuit comprising:

an array of semiconductor memory cells formed in a semiconductor substrate having at least one surface, the array comprising;

said semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a transistor comprising a source region, a first floating body region, a drain region, and a gate, and

a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region,

a first control circuit configured to provide electrical signals to said anode region, and

a second control circuit configured to provide electrical signals to said transistor to access said memory cell;

wherein;

a state of said memory cell is stored in said first floating body region,

said first floating body region and said second floating body region are common,

said silicon controlled rectifier device maintains a state of said memory cell,

said transistor is usable to access said memory cell, and

wherein said anode region is commonly connected to at least two of said memory cells.

37. The integrated circuit of claim 36, wherein said first control circuit provides electrical signals to said anode region to maintain the state of said memory cells connected to said anode region.

38. The integrated circuit of claim 37, wherein said electrical signals to said anode region are constant voltage biases.

39. The integrated circuit of claim 37, wherein said electrical signals to said anode region are periodic pulses of voltage.

40. The integrated of claim 37, wherein said electrical signals to said anode region result in at least two stable states.

41. The integrated circuit of claim 36, wherein said transistor is formed in a fin structure.