VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS
First Claim
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1. A semiconductor device, comprising:
- a semiconductor substrate;
a gate electrode layer structure that includes a plurality of spaced-apart gate electrode layers stacked on an upper surface of the semiconductor substrate;
a plurality of channel regions penetrating the gate electrode layers;
a plurality of dummy channel regions penetrating at least the lowermost of the gate electrode layers; and
a substrate insulating layer between the semiconductor substrate and the dummy channel regions.
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Abstract
A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.
54 Citations
38 Claims
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1. A semiconductor device, comprising:
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a semiconductor substrate; a gate electrode layer structure that includes a plurality of spaced-apart gate electrode layers stacked on an upper surface of the semiconductor substrate; a plurality of channel regions penetrating the gate electrode layers; a plurality of dummy channel regions penetrating at least the lowermost of the gate electrode layers; and a substrate insulating layer between the semiconductor substrate and the dummy channel regions. - View Dependent Claims (2, 3, 4, 5, 6, 9, 10)
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7-8. -8. (canceled)
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11-16. -16. (canceled)
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17. A semiconductor device, comprising:
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a semiconductor substrate having an upper surface that defines a horizontal plane; a gate electrode layer structure that includes a plurality of gate electrode layers and a plurality of insulating layers that are alternately stacked in a vertical direction on the upper surface of the semiconductor substrate; a plurality of dummy channel regions that penetrate the gate electrode layer structure, the dummy channel regions comprising respective annular channel layers that penetrate a lowermost of the gate electrode layers; and a plurality of channel regions that penetrate the gate electrode layer structure, the channel regions comprising respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on an upper surface of the respective epitaxial patterns, wherein the dummy channel regions are spaced apart from the semiconductor substrate. - View Dependent Claims (18, 19, 20, 21, 22, 28)
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23-27. -27. (canceled)
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29-30. -30. (canceled)
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31. A semiconductor memory device, comprising:
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a semiconductor substrate having an upper surface that has a plurality of recesses therein; a substrate insulating layer that includes a plurality of substrate insulating patterns in the respective recesses; a gate electrode layer structure on the upper surface of the semiconductor substrate; and a plurality of dummy channel regions vertically penetrating the gate electrode layer structure, wherein the dummy channel regions directly contact the substrate insulating layer. - View Dependent Claims (32, 33, 37)
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34-36. -36. (canceled)
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38-59. -59. (canceled)
Specification