VERTICAL MEMORY DEVICES HAVING DUMMY CHANNEL REGIONS

• US 20170040337A1
• Filed: 01/05/2016
• Published: 02/09/2017
• Est. Priority Date: 08/07/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Chang Seok Kang, Hanmei Choi, Jae Duk Lee, Jae Woo Lim, Jong Won Kim, Seung Hyun Lim, Woo Sung Lee, Young Woo Park
• Inventors: KIM, Jong Won, LIM, Seung Hyun, BAE, Dae Hoon, EUN, Dong Seog, LEE, Jae Duk, LIM, Jae Woo, CHOI, HanMei, KANG, Chang Seok, PARK, Young Woo, LEE, Woo Sung
• Granted Patent: US 9,716,104 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a gate electrode layer structure that includes a plurality of spaced-apart gate electrode layers stacked on an upper surface of the semiconductor substrate;

a plurality of channel regions penetrating the gate electrode layers;

a plurality of dummy channel regions penetrating at least the lowermost of the gate electrode layers; and

a substrate insulating layer between the semiconductor substrate and the dummy channel regions.

2. The semiconductor device of claim 1, wherein the substrate insulating layer comprises a plurality of substrate insulating patterns, wherein the semiconductor substrate includes a plurality of recesses, and wherein the substrate insulating patterns are formed in respective ones of the recesses.

3. The semiconductor device of claim 1, wherein the dummy channel regions extend below the upper surface of the semiconductor substrate and directly contact the substrate insulating layer.

4. The semiconductor device of claim 1, wherein the dummy channel regions comprise respective annular channel regions that penetrate a lowermost one of the gate electrode layers.

5. The semiconductor device of claim 4, wherein the channel regions comprise respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on upper surfaces of the respective epitaxial patterns.

6. The semiconductor device of claim 5, wherein the epitaxial patterns penetrate a lowermost one of the gate electrode layers.

9. The semiconductor device of claim 1, further comprising a plurality of bit lines, wherein the channel regions are electrically connected to respective ones of the bit lines and wherein the dummy channel regions are not electrically connected to any of the bit lines.

10. The semiconductor device of claim 1, wherein the dummy channel regions penetrate a first region of the gate electrode layer structure that has a stepped structure, and wherein the channel regions are spaced-apart from the first region of the gate electrode layer structure.

7-8. -8. (canceled)

11-16. -16. (canceled)

17. A semiconductor device, comprising:

a semiconductor substrate having an upper surface that defines a horizontal plane;

a gate electrode layer structure that includes a plurality of gate electrode layers and a plurality of insulating layers that are alternately stacked in a vertical direction on the upper surface of the semiconductor substrate;

a plurality of dummy channel regions that penetrate the gate electrode layer structure, the dummy channel regions comprising respective annular channel layers that penetrate a lowermost of the gate electrode layers; and

a plurality of channel regions that penetrate the gate electrode layer structure, the channel regions comprising respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on an upper surface of the respective epitaxial patterns,

wherein the dummy channel regions are spaced apart from the semiconductor substrate.

18. The semiconductor device of claim 17, wherein bottom surfaces of the respective dummy channel regions extend below a bottom surface of the gate electrode layer structure.

19. The semiconductor device of claim 18, further comprising a substrate insulating layer that includes a plurality of substrate insulating patterns that are provided in respective recesses in the upper surface of the semiconductor substrate.

20. The semiconductor device of claim 19, wherein bottom surfaces of the respective dummy channel regions directly contact the substrate insulating layer.

21. The semiconductor device of claim 17, wherein the channel regions comprise respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on upper surfaces of the respective epitaxial patterns.

22. The semiconductor device of claim 21, wherein the epitaxial patterns of the respective channel regions penetrate a lowermost one of the gate electrode layers.

28. The semiconductor device of claim 17, further comprising a plurality of bit lines, wherein the channel regions are electrically connected to respective ones of the bit lines and wherein the dummy channel regions are not electrically connected to any of the bit lines.

23-27. -27. (canceled)

29-30. -30. (canceled)

31. A semiconductor memory device, comprising:

a semiconductor substrate having an upper surface that has a plurality of recesses therein;

a substrate insulating layer that includes a plurality of substrate insulating patterns in the respective recesses;

a gate electrode layer structure on the upper surface of the semiconductor substrate; and

a plurality of dummy channel regions vertically penetrating the gate electrode layer structure, wherein the dummy channel regions directly contact the substrate insulating layer.

32. The semiconductor device of claim 31, wherein the dummy channel regions have respective lower surfaces that are below the upper surface of the semiconductor substrate.

33. The semiconductor device of claim 31, further comprising a plurality of channel regions, the channel regions comprising respective epitaxial patterns on the semiconductor substrate and respective annular channel regions on upper surfaces of the respective epitaxial patterns.

37. The semiconductor device of claim 33, wherein the epitaxial patterns directly contact the semiconductor substrate.

34-36. -36. (canceled)

38-59. -59. (canceled)