SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

• US 20170040371A1
• Filed: 04/09/2015
• Published: 02/09/2017
• Est. Priority Date: 04/21/2014
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Izuhara, Kunihiko
• Granted Patent: US 10,217,785 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

There is provided a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon, and a second substrate having a plurality of signal processing circuits formed thereon so as to be arranged through a scribe region. The first substrate and the second substrate are stacked.

Claims

1. A solid-state imaging device including:

a first substrate having a pixel circuit including a pixel array unit formed thereon; and

a second substrate having a plurality of signal processing circuits formed thereon, wherein the plurality of signal processing circuits are arranged adjacent to one another and include a spacing region therebetween, and

wherein the first substrate and the second substrate are stacked.

2. The solid-state imaging device according to claim 1, wherein each of the signal processing circuits have a same set of functions.

3. The solid-state imaging device according to claim 1, wherein the same set of functions includes operating as a same signal processing circuit.

4. The solid-state imaging device according to claim 2, wherein a function to be enabled and a function to be disabled are configured in each of the signal processing circuits in response to one or more external signals.

5. The solid-state imaging device according to claim 1, wherein a first signal processing circuit of the plurality of signal processing circuits is configured to generate first pixel data based on a pixel signal of a pixel in a first region of the pixel array unit, and wherein a second signal processing circuit of the plurality of signal processing circuits is configured to generate second pixel data based on a pixel signal of a pixel in a second region different from the first region of the pixel array unit.

6. The solid-state imaging device according to claim 1, wherein a first signal processing circuit of the plurality of signal processing circuits and a second signal processing circuit of the plurality of signal processing circuits are electrically connected.

7. The solid-state imaging device according to claim 6, wherein the first signal processing circuit and the second signal processing circuit are electrically connected through a first wiring layer formed on the second substrate.

8. The solid-state imaging device according to claim 7, wherein the first wiring layer is formed on a top layer of a wiring layer of the second substrate.

9. The solid-state imaging device according to claim 7, further comprising:

a first moisture-resistant structure that surrounds at least a part of a periphery of the first signal processing circuit; and

a second moisture-resistant structure that surrounds at least a part of a periphery of the second signal processing circuit.

10. The solid-state imaging device according to claim 9, wherein the first signal processing circuit and the second signal processing circuit have a common circuit pattern, wherein the first wiring layer is formed on the top layer of the wiring layer of the second substrate, and includes a top layer of the first moisture-resistant structure and a top layer of the second moisture-resistant structure, wherein the top layer of the first moisture-resistant structure, and a first wall connecting the top layer of the first moisture-resistant structure and a layer one below the top layer are not formed at a first portion through which a wiring of the first wiring layer of the first moisture-resistant structure passes, and wherein the top layer of the second moisture-resistant structure, a second wall connecting the top layer of the second moisture-resistant structure, and a layer one below the top layer are not formed at a second portion through which a wiring of the first wiring layer of the second moisture-resistant structure passes.

11. The solid-state imaging device according to claim 10, wherein the first wall is not formed at a third portion of the first moisture-resistant structure corresponding to the second portion of the second moisture-resistant structure, and wherein the second wall is not formed at a fourth portion of the second moisture-resistant structure corresponding to the first portion of the first moisture-resistant structure.

12. The solid-state imaging device according to claim 10, wherein a wiring layer, except for the first wiring layer of the second substrate, is formed by a one-shot exposure, and the first wiring layer is formed by a separate exposure.

13. The solid-state imaging device according to claim 10, wherein interlayer insulation films of second and subsequent wiring layers are made of a low-K film, the second wiring layer being one below the first wiring layer, and wherein an interlayer insulation film above the second wiring layer is made of an insulation film having a water resistance higher than that of the low-K film.

14. The solid-state imaging device according to claim 7, further comprising a moisture-resistant structure that surrounds at least a part of a periphery of the second substrate.

15. The solid-state imaging device according to claim 14, wherein at least a portion of one or more layers of the respective signal processing circuits are formed by a one-shot exposure, and wherein a layer having a moisture-resistant structure formed thereon is formed by the separate exposure.

16. The solid-state imaging device according to claim 6, wherein the first signal processing circuit and the second signal processing circuit are electrically connected through a wiring formed on the first substrate.

17. The solid-state imaging device according to claim 16, wherein the wiring formed on the first substrate is formed in an area outside of the pixel array unit, and

wherein the first signal processing circuit and the second signal processing circuit are connected to the wiring formed on the first substrate through a via formed on the first substrate.

18. The solid-state imaging device according to claim 6, wherein the first signal processing circuit and the second signal processing circuit are electrically connected to each other in an area that is external to the solid-state imaging device.

19. The solid-state imaging device according to claim 18, wherein the solid-state imaging device is mounted to a package and the first signal processing circuit and the second signal processing circuit are electrically connected through a conductive pattern on the package.

20. The solid-state imaging device according to claim 18, wherein signal lines of a same analog signal of the first signal processing circuit and the second signal processing circuit are electrically connected, in an area that is external to the solid-state imaging device.

21. The solid-state imaging device according to claim 6, wherein the first signal processing circuit and the second signal processing circuit are electrically connected to a substrate by one or more bond wires, and wherein the substrate is at least one of provided in the solid-state imaging device, provided in a same package, and provided outside the package.

22. The solid-state imaging device according to claim 6, wherein the first signal processing circuit is configured to generate first pixel data based on a pixel signal of a pixel in a first region of the pixel array unit, and supply the generated first pixel data to the second signal processing circuit, and wherein the second signal processing circuit is configured to generate second pixel data based on a pixel signal of a pixel in a second region different from the first region of the pixel array unit, and combine the generated second pixel data with the first pixel data.

23. The solid-state imaging device according to claim 6, wherein the first signal processing circuit is configured to generate first pixel data based on a pixel signal of a pixel in a predetermined region of the pixel array unit, and supply the generated first pixel data to the second signal processing circuit, and wherein the second signal processing circuit is configured to generate second pixel data based on a pixel signal of a pixel of the pixel array unit in the same region as that of the first signal processing circuit, and generate third pixel data by adding the first pixel data and the second pixel data.

24. The solid-state imaging device according to claim 1, wherein a third substrate is stacked on a surface on an opposite side of a surface adjacent to the first substrate of the second substrate.

25. The solid-state imaging device according to claim 24, further comprising a memory on the third substrate that is configured to store pixel data obtained by analog-to-digital (AD) converting of a pixel signal of each pixel in the pixel array unit.

26. The solid-state imaging device according to claim 1, further comprising an analog-to-digital (AD) conversion unit on the second substrate, wherein the AD conversion unit is configured to convert a pixel signal of each pixel in the pixel array unit in units of columns of the pixel array unit.

27. The solid-state imaging device according to claim 1, further comprising an analog-to-digital (AD) conversion unit on the second substrate, wherein the AD conversion unit is configured to convert a pixel signal of each pixel in the pixel array unit in units of regions that include a two-dimensional array of pixels of a predetermined number in the pixel array unit.

28. The solid-state imaging device according to claim 1, wherein the pixel circuit is formed by a separate exposure, and wherein at least a portion of one or more layers of respective signal processing circuits are formed by a one-shot exposure.

29. The solid-state imaging device according to claim 1, wherein a first signal processing circuit of the plurality of signal processing circuits and a second signal processing circuit of the plurality of signal processing circuits are formed by a same one-shot exposure.

30. The solid-state imaging device according to claim 1, wherein the spacing region between the plurality of signal processing circuits is a scribe region.

31. A manufacturing method of a solid-state imaging device, including:

forming a pixel circuit including a pixel array unit so as to be two-dimensionally arranged through a scribe region on a first semiconductor substrate, by using one or more separate exposures;

forming a signal processing circuit that processes a pixel signal of each pixel in the pixel array unit so as to be two-dimensionally arranged through a scribe region on a second semiconductor substrate, by using a one-shot exposure;

stacking the first semiconductor substrate and the second semiconductor substrate such that the scribe region of the first semiconductor substrate overlaps the scribe region of the second semiconductor substrate; and

cutting a semiconductor substrate including the first semiconductor substrate and the second semiconductor substrate that are stacked, along the scribe region of the first semiconductor substrate.

32. The manufacturing method of a solid-state imaging device according to claim 31, wherein the signal processing circuit includes a first signal processing circuit and a second signal processing circuit arranged adjacent to one another and include the scribe region of the second semiconductor substrate therebetween, and wherein a wiring layer that electrically connects the first signal processing circuit and the second signal processing circuit, which are disposed in the same solid-state imaging device, is formed on the second semiconductor substrate.

33. The manufacturing method of a solid-state imaging device according to claim 32, wherein the wiring layer is formed on a top layer of a wiring layer of the second semiconductor substrate.

34. The manufacturing method of a solid-state imaging device according to claim 32, further including:

forming a first moisture-resistant structure that surrounds at least a part of a periphery of the first signal processing circuit; and

forming a second moisture-resistant structure that surrounds at least a part of a periphery of the second signal processing circuit.

35. The manufacturing method of a solid-state imaging device according to claim 32, further including:

forming a moisture-resistant structure that surrounds at least a part of an outer periphery of the first and second signal processing circuits which are disposed on the same solid-state imaging device.

36. The manufacturing method of a solid-state imaging device according to claim 31, wherein the signal processing circuit includes a first signal processing circuit and a second signal processing circuit arranged adjacent to one another and include the scribe region of the second semiconductor substrate therebetween, and wherein a wiring and a via for electrically connecting the first signal processing circuit and the second signal processing circuit, which are disposed on the same solid-state imaging device, are formed on the first semiconductor substrate.

37. An electronic apparatus including:

a solid-state imaging device including a first substrate having a pixel circuit including a pixel array unit formed thereon and a second substrate having a plurality of signal processing circuits formed thereon, wherein the plurality of signal processing circuits are arranged adjacent to one another and include a spacing region therebetween, and wherein the first substrate and the second substrate are stacked.