PIXEL STRUCTURE
First Claim
1. A pixel structure, comprising:
- a metal oxide semiconductor layer comprising a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern comprises a first doping region, a second doping region and a channel region, the first doping region and the second doping region are disposed respectively on two sides of the channel region, and the second semiconductor pattern comprises a contact portion and an electrode portion;
a first insulating layer comprising a first gate insulation pattern and a first capacitance dielectric pattern, wherein the first gate insulation pattern is disposed on the first semiconductor pattern of the metal oxide semiconductor layer, and the first capacitance dielectric pattern is disposed on the second semiconductor pattern of the metal oxide semiconductor layer;
a second insulating layer comprising a second gate insulation pattern and a second capacitance dielectric pattern, wherein the second gate insulation pattern is disposed on the first gate insulation pattern of the first insulating layer, and the second capacitance dielectric pattern is disposed on the first capacitance dielectric pattern of the first insulating layer;
a first conductive layer comprising a gate and an electrode pattern, wherein the gate is disposed on the second gate insulation pattern of the second insulating layer, and the electrode pattern is disposed on the second capacitance dielectric pattern of the second insulating layer;
a passivation layer covering the metal oxide semiconductor layer and the first conductive layer, and having a first opening through which the first doping region of the first semiconductor pattern is exposed, a second opening through which the second doping region of the first semiconductor pattern is exposed, a third opening through which the contact portion of the second semiconductor pattern is exposed, and a fourth opening through which the electrode pattern of the first conductive layer is exposed;
a second conductive layer disposed on the passivation layer and comprising a first electrode, a second electrode and a second electrode extending portion connected with the second electrode;
wherein;
the first electrode is electrically connected to the first doping region of the first semiconductor pattern through the first opening;
the second electrode is electrically connected to the second doping region of the first semiconductor pattern through the second opening;
the second electrode is electrically connected to the contact portion of the second semiconductor pattern through the third opening;
the gate, the first semiconductor pattern, the first electrode and the second electrode form an active element;
the second semiconductor pattern partially overlaps the electrode pattern of the first conductive layer and is coupled with the electrode pattern of the first conductive layer to form a first storage capacitor; and
the electrode pattern of the first conductive layer partially overlaps the second electrode extending portion and is coupled with the second electrode extending portion to form a second storage capacitor; and
a pixel electrode electrically connected to the second electrode.
1 Assignment
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Accused Products
Abstract
A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern. The second semiconductor pattern, the electrode pattern and the second electrode form a storage capacitor.
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Citations
20 Claims
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1. A pixel structure, comprising:
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a metal oxide semiconductor layer comprising a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern comprises a first doping region, a second doping region and a channel region, the first doping region and the second doping region are disposed respectively on two sides of the channel region, and the second semiconductor pattern comprises a contact portion and an electrode portion; a first insulating layer comprising a first gate insulation pattern and a first capacitance dielectric pattern, wherein the first gate insulation pattern is disposed on the first semiconductor pattern of the metal oxide semiconductor layer, and the first capacitance dielectric pattern is disposed on the second semiconductor pattern of the metal oxide semiconductor layer; a second insulating layer comprising a second gate insulation pattern and a second capacitance dielectric pattern, wherein the second gate insulation pattern is disposed on the first gate insulation pattern of the first insulating layer, and the second capacitance dielectric pattern is disposed on the first capacitance dielectric pattern of the first insulating layer; a first conductive layer comprising a gate and an electrode pattern, wherein the gate is disposed on the second gate insulation pattern of the second insulating layer, and the electrode pattern is disposed on the second capacitance dielectric pattern of the second insulating layer; a passivation layer covering the metal oxide semiconductor layer and the first conductive layer, and having a first opening through which the first doping region of the first semiconductor pattern is exposed, a second opening through which the second doping region of the first semiconductor pattern is exposed, a third opening through which the contact portion of the second semiconductor pattern is exposed, and a fourth opening through which the electrode pattern of the first conductive layer is exposed; a second conductive layer disposed on the passivation layer and comprising a first electrode, a second electrode and a second electrode extending portion connected with the second electrode;
wherein;
the first electrode is electrically connected to the first doping region of the first semiconductor pattern through the first opening;
the second electrode is electrically connected to the second doping region of the first semiconductor pattern through the second opening;
the second electrode is electrically connected to the contact portion of the second semiconductor pattern through the third opening;
the gate, the first semiconductor pattern, the first electrode and the second electrode form an active element;
the second semiconductor pattern partially overlaps the electrode pattern of the first conductive layer and is coupled with the electrode pattern of the first conductive layer to form a first storage capacitor; and
the electrode pattern of the first conductive layer partially overlaps the second electrode extending portion and is coupled with the second electrode extending portion to form a second storage capacitor; anda pixel electrode electrically connected to the second electrode. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A pixel structure, comprising:
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a metal oxide semiconductor layer comprising a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern comprises a first doping region, a second doping region and a channel region, the first doping region and the second doping region are disposed respectively on two sides of the channel region, and the second semiconductor pattern comprises a contact portion and an electrode portion; a first insulating layer comprising a first gate insulation pattern and a first capacitance dielectric pattern, wherein the first gate insulation pattern is disposed on the first semiconductor pattern of the metal oxide semiconductor layer, and the first capacitance dielectric pattern is disposed on the second semiconductor pattern of the metal oxide semiconductor layer; a second insulating layer comprising a second gate insulation pattern and a second capacitance dielectric pattern, wherein the second gate insulation pattern is disposed on the first gate insulation pattern of the first insulating layer, and the second capacitance dielectric pattern is disposed on the first capacitance dielectric pattern of the first insulating layer; a conductive pattern disposed above the second semiconductor pattern and between the first capacitance dielectric pattern of the first insulating layer and the second capacitance dielectric pattern of the second insulating layer; a first conductive layer comprising a gate and an electrode pattern, wherein the gate is disposed on the second gate insulation pattern of the second insulating layer, the electrode pattern is disposed on the second capacitance dielectric pattern of the second insulating layer, the first doping region and the second doping region of the first semiconductor pattern are exposed, and the contact portion of the second semiconductor pattern is exposed; a passivation layer covering the metal oxide semiconductor layer and the first conductive layer and having a first opening through which the first doping region of the first semiconductor pattern is exposed, a second opening through which the second doping region of the first semiconductor pattern is exposed, a third opening through which the contact portion of the second semiconductor pattern is exposed, and fourth opening through which the electrode pattern of the first conductive layer is exposed; a second conductive layer disposed on the passivation layer and comprising a first electrode and a second electrode, wherein the first electrode is electrically connected to the first doping region of the first semiconductor pattern through the first opening;
the second electrode is electrically connected to the second doping region of the first semiconductor pattern through the second opening;
the gate, the first semiconductor pattern, the first electrode and the second electrode form an active element;
the second electrode is electrically connected to the contact portion of the second semiconductor pattern through the third opening;
the second semiconductor pattern partially overlaps the conductive pattern and is coupled with the conductive pattern to form a storage capacitor; and
the conductive pattern partially overlaps the electrode pattern of the first conductive layer and is coupled with the electrode pattern of the first conductive layer to form another storage capacitor; anda pixel electrode electrically connected to the second electrode. - View Dependent Claims (8, 9, 10, 11)
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12. A layered structure usable for a pixel structure, comprising:
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a metal oxide semiconductor layer comprising a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern comprises a first doping region, a second doping region and a channel region, the first doping region and the second doping region are disposed respectively on two sides of the channel region, and the second semiconductor pattern comprises a contact portion and an electrode portion; a first conductive layer comprising a gate and an electrode pattern, wherein the gate is disposed above the first semiconductor pattern, and at least one gate insulation pattern is formed between the gate and the first semiconductor pattern;
the electrode pattern is disposed above the second semiconductor pattern, and at least one capacitance dielectric pattern is formed between the electrode pattern and the second semiconductor pattern, such that the first doping region and the second doping region of the first semiconductor pattern are exposed, and the contact portion of the second semiconductor pattern is exposed;a passivation layer covering the metal oxide semiconductor layer and the first conductive layer and having a first opening through which the first doping region of the first semiconductor pattern is exposed, a second opening through which the second doping region of the first semiconductor pattern is exposed, a third opening through which the contact portion is exposed, and a fourth opening through which the electrode pattern is exposed; a second conductive layer disposed on the passivation layer and comprising a first electrode and a second electrode, wherein the first electrode is electrically connected to the first doping region of the first semiconductor pattern through the first opening;
the second electrode is electrically connected to the second doping region of the first semiconductor pattern through the second opening;
the gate of the first conductive layer, the first semiconductor pattern, the first electrode and the second electrode form an active element;
the second electrode is electrically connected to the contact portion of the second semiconductor pattern through the third opening; anda pixel electrode electrically connected to the second electrode, wherein the second semiconductor pattern, the electrode pattern and the second electrode are formed in a partially overlapping mode to form at least two storage capacitors therebetween. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification