SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

• US 20170040445A1
• Filed: 10/25/2016
• Published: 02/09/2017
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: NAKAZAWA, Yoshito, YATSUDA, Yuji
• Granted Patent: US 9,837,528 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

Claims

1. A semiconductor device including a semiconductor chip, the semiconductor chip comprising:

a field-effect transistor including a drain region, a source region, a first gate electrode and a second gate electrode; and

a protective diode,

wherein the source region is electrically connected to one electrode of the protective diode, and

wherein the second gate electrode is electrically connected to another electrode of the protective diode.

2. A semiconductor device according to the claim 1,

wherein a trench is formed in a semiconductor substrate,

wherein a first gate insulating film is formed in the trench and disposed at a lower part of the trench,

wherein the first gate electrode is formed over the first gate insulating film in the trench and disposed at the lower part of the trench,

wherein a second gate insulating film is formed in the trench and disposed at an upper part of the trench,

wherein a second gate electrode is formed over the second gate insulating film in the trench and disposed at the upper part of the trench, and

wherein a thickness of the first gate insulating film is thicker than a thickness of the second gate insulating film.

3. A semiconductor device according to the claim 2,

wherein each of the first gate electrode and the protective diode includes a first polysilicon film, and

wherein the second gate electrode includes a second polysilicon film.

4. A semiconductor device according to the claim 3,

wherein the protective diode is located outside of the trench.

5. A semiconductor device according to the claim 4,

wherein the first polysilicon film is formed of an n-type impurity,

wherein the second polysilicon film is formed of the n-type impurity, and

wherein the protective diode includes an n-type impurity region and a p-type impurity region.

6. A semiconductor device according to the claim 5,

wherein the source region is formed of the n-type impurity, is formed in the semiconductor substrate and is formed near the upper part of the trench, and

wherein the drain region is formed of the n-type impurity, is formed in the semiconductor substrate and is formed near the lower part of the trench.